DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-9, 12-14, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yim et al. (U.S. Patent Application Publication No. 2024/0395720).
Regarding to claim 1, Yim teaches an integrated circuit die stack comprising:
a plurality of first integrated circuit dice disposed in a first tier of the integrated circuit die stack (Fig. 1, first integrated circuit dice 130/140/195 disposed in first tear 181/160), the plurality of the first integrated circuit dice comprising a first integrated circuit die (Fig. 1, element 130; [0036], line 4) and a bridge die (Fig. 1, element 195; [0036], line 7); and
a plurality of second integrated circuit dice disposed in a second tier of the integrated circuit die stack (Fig. 1, second integrated circuit dice 210/220 disposed in second tear 161), the plurality of the second integrated circuit dice stacked vertically above the plurality of the first integrated circuit dice of the first tier (Fig. 1), the plurality of the second integrated circuit dice comprising a second integrated circuit die and a third integrated circuit die (Fig. 1, second integrated circuit dice comprising second integrated circuit die 210 and third integrated circuit die 220),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 1, the bridge die 195 couples with both the second integrated circuit die 210 and third integrated circuit die 220).
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Regarding to claim 2, Yim teaches the bridge die comprises routing connections between the second and third integrated circuit dice (Fig. 1, element 198B; [0063], line 4).
Regarding to claim 3, Yim teaches the routing connections are coupled by a plurality of hybrid bonds of the second and third integrated circuit dice (Fig. 1, [0036], last 3 lines).
Regarding to claim 8, Yim teaches a plurality of hybrid bonds coupling the first integrated circuit die with the second integrated circuit die and/or the third integrated circuit die (Fig. 1, [0036], last 3 lines).
Regarding to claim 9, Yim teaches the second integrated circuit die covers an entirety of the first integrated circuit die (Fig. 1, the second integrated circuit die 210 covers an entirety of the first integrated circuit die 130 in top-down view).
Regarding to claim 12, Yim teaches an integrated circuit die package assembly comprising:
a package substrate (Fig. 1A, element 110); and
an integrated circuit die stack disposed above the package substrate within the integrated circuit die package assembly (Fig. 1), the integrated circuit die stack comprising:
a first integrated circuit die (Fig. 1, element 130; [0036], line 4) and a bridge die (Fig. 1, element 195; [0036], line 7) disposed in a first tier (Fig. 1, element 181/160) of the die stack; and
a second integrated circuit die (Fig. 1, element 210) and a third integrated circuit die (Fig. 1, element 220) disposed in a second tier (Fig. 1, element 161) that is stacked vertically above the first tier (Fig. 1),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 1, the bridge die 195 couples with both the second integrated circuit die 210 and third integrated circuit die 220).
Regarding to claim 13, Yim teaches the bridge die comprises routing connections between the second and third integrated circuit dice (Fig. 1, element 198B; [0063], line 4).
Regarding to claim 14, Yim teaches the routing connections are coupled by a plurality of hybrid bonds of the second and third integrated circuit dice (Fig. 1).
Regarding to claim 18, Yim teaches the bridge die comprises a plurality of through silicon vias (Fig. 1, element 197, [0063], lines 1-2).
Regarding to claim 19, Yim teaches the plurality of the integrated circuit dice of the first tier are mounted on an interposer or a package substrate (Fig. 1).
Regarding to claim 20, Yim teaches method for manufacturing an integrated circuit die stack, the method comprising (note that the method steps are not claimed to impart in a specific order):
mounting the plurality of the dice of a first tier on a carrier, the plurality of dice of the first tier comprising a bridge die (Fig. 1, mounting the plurality of the dice 130/140/195 of a first tier on carrier 110, the plurality of dice of the first tier comprising bridge die element 195);
arranging a plurality of the dice of the second tier on top of the dice of the first tier (Fig. 1, arranging plurality of the dice 210/220 of the second tier on top of the dice of the first tier);
forming an integrated circuit die stack by connecting the dice of the first tier with the dice of the second tier, wherein the connecting comprises connecting the bridge die with at least two dice of the second tier (Fig. 1, forming integrated circuit die stack by connecting the dice 30/140/195 of the first tier with the dice 210/220 of the second tier, the connecting comprises connecting the bridge die 195 with two dice 210 and 220 of the second tier); and
mounting the integrated circuit die stack die stack on a package substrate (Fig. 1).
Claims 1-3, 6, 8-9, 12-14, 17, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Brun et al. (U.S. Patent No. 12,368,089).
Regarding to claim 1, Brun teaches an integrated circuit die stack comprising:
a plurality of first integrated circuit dice disposed in a first tier of the integrated circuit die stack (Fig. 1, column 6, lines 10-12, first integrated circuit dice 106A/B disposed in first tear 108), the plurality of the first integrated circuit dice comprising a first integrated circuit die (Fig. 1, element 106A/left) and a bridge die (Fig. 1, element 106B); and
a plurality of second integrated circuit dice disposed in a second tier of the integrated circuit die stack (Fig. 1, column 4, lined 58-62, second integrated circuit dice 102 disposed in second tear 130), the plurality of the second integrated circuit dice stacked vertically above the plurality of the first integrated circuit dice of the first tier (Fig. 1), the plurality of the second integrated circuit dice comprising a second integrated circuit die and a third integrated circuit die (Fig. 1, second integrated circuit dice comprising second integrated circuit die 102/left and third integrated circuit die 102/right),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 1, the bridge die 106-B couples with both the second integrated circuit die 102/left and third integrated circuit die 102/right).
Regarding to claim 2, Brun teaches the bridge die comprises routing connections between the second and third integrated circuit dice (Fig. 1).
Regarding to claim 3, Brun teaches the routing connections are coupled by a plurality of hybrid bonds of the second and third integrated circuit dice (Fig. 1, column 8, line 43).
Regarding to claim 6, Brun teaches the bridge die comprises passive integrated devices (column 6, lines 21-22).
Regarding to claim 8, Brun teaches a plurality of hybrid bonds coupling the first integrated circuit die with the second integrated circuit die and/or the third integrated circuit die (Fig. 1).
Regarding to claim 9, Brun teaches the second integrated circuit die covers an entirety of the first integrated circuit die (Fig. 1, the second integrated circuit die 120/left covers an entirety of the first integrated circuit die 106A/left).
Regarding to claim 12, Brun teaches an integrated circuit die package assembly comprising:
a package substrate (Fig. 1, element 112); and
an integrated circuit die stack disposed above the package substrate within the integrated circuit die package assembly (Fig. 1), the integrated circuit die stack comprising:
a first integrated circuit die (Fig. 1, element 106A/left) and a bridge die (Fig. 1, element 106B) disposed in a first tier (Fig. 1, element 108) of the die stack; and
a second integrated circuit die (Fig. 1, element 102/left) and a third integrated circuit die (Fig. 1, element 102/right) disposed in a second tier (Fig. 1, element 130) that is stacked vertically above the first tier (Fig. 1),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 1, the bridge die 106B couples with both the second integrated circuit die 102/left and third integrated circuit die 102/right).
Regarding to claim 13, Brun teaches the bridge die comprises routing connections between the second and third integrated circuit dice (Fig. 1).
Regarding to claim 14, Brun teaches the routing connections are coupled by a plurality of hybrid bonds of the second and third integrated circuit dice (Fig. 1).
Regarding to claim 17, Brun teaches the bridge die comprises passive integrated devices (column 6, lines 21-22).
Regarding to claim 19, Brun teaches the plurality of the integrated circuit dice of the first tier are mounted on an interposer or a package substrate (Fig. 1).
Regarding to claim 20, Brun teaches method for manufacturing an integrated circuit die stack, the method comprising (note that the method steps are not claimed to impart in a specific order):
mounting the plurality of the dice of a first tier on a carrier, the plurality of dice of the first tier comprising a bridge die (Fig. 1, mounting the plurality of the dice 106 of a first tier on carrier 112, the plurality of dice of the first tier comprising bridge die element 106B);
arranging a plurality of the dice of the second tier on top of the dice of the first tier (Fig. 1, arranging plurality of the dice 102 of the second tier on top of the dice of the first tier);
forming an integrated circuit die stack by connecting the dice of the first tier with the dice of the second tier, wherein the connecting comprises connecting the bridge die with at least two dice of the second tier (Fig. 1, forming integrated circuit die stack by connecting the dice 106 of the first tier with the dice 102 of the second tier, the connecting comprises connecting the bridge die 106B with two dice 102/left and 102/right of the second tier); and
mounting the integrated circuit die stack die stack on a package substrate (Fig. 1).
Claims 1, 8, 12, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Karhade et al. (U.S. Patent Application Publication No. 2024/0063066).
Regarding to claim 1, Karhade teaches an integrated circuit die stack comprising:
a plurality of first integrated circuit dice disposed in a first tier of the integrated circuit die stack (Fig. 2A, first integrated circuit dice 104-4/104-5 disposed in first tear 102-2), the plurality of the first integrated circuit dice comprising a first integrated circuit die (Fig. 2A, element 104-5; [0083], lines 9-10) and a bridge die (Fig. 2A, element 104-4; [0080], line 4); and
a plurality of second integrated circuit dice disposed in a second tier of the integrated circuit die stack (Fig. 2A, second integrated circuit dice 104-6/104-7 disposed in second tear 102-3), the plurality of the second integrated circuit dice stacked vertically above the plurality of the first integrated circuit dice of the first tier (Fig. 2A), the plurality of the second integrated circuit dice comprising a second integrated circuit die and a third integrated circuit die (Fig. 2A, second integrated circuit dice comprising second integrated circuit die 104-6 and third integrated circuit die 104-7),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 2A, the bridge die 104-4 couples with both the second integrated circuit die 104-6 and third integrated circuit die 104-7).
Regarding to claim 8, Karhade teaches a plurality of hybrid bonds coupling the first integrated circuit die with the second integrated circuit die and/or the third integrated circuit die (Fig. 2A).
Regarding to claim 12, Karhade teaches an integrated circuit die package assembly comprising:
a package substrate (Fig. 2A, element 118); and
an integrated circuit die stack disposed above the package substrate within the integrated circuit die package assembly (Fig. 2A), the integrated circuit die stack comprising:
a first integrated circuit die (Fig. 2A, element 104-5; [0083], lines 9-10) and a bridge die (Fig. 2A, element 104-4; [0080], line 4) disposed in a first tier (Fig. 2A, element 102-2) of the die stack; and
a second integrated circuit die (Fig. 2A, element 104-6; [0083], lines 9-10) and a third integrated circuit die (Fig. 2A, element 104-7; [0083], lines 9-10) disposed in a second tier (Fig. 2A, element 102-3) that is stacked vertically above the first tier (Fig. 2A),
wherein the bridge die couples with both the second integrated circuit die and the third integrated circuit die (Fig. 2A, the bridge die 104-4 couples with both the second integrated circuit die 104-6 and third integrated circuit die 104-7).
Regarding to claim 18, Karhade teaches the bridge die comprises a plurality of through silicon vias (Fig. 2A, [0078], lines 2-3).
Regarding to claim 19, Karhade teaches the plurality of the integrated circuit dice of the first tier are mounted on an interposer or a package substrate (Fig. 2A, element 116/103).
Regarding to claim 20, Karhade teaches method for manufacturing an integrated circuit die stack, the method comprising:
mounting the plurality of the dice of a first tier on a carrier, the plurality of dice of the first tier comprising a bridge die (Fig. 2A, mounting the plurality of the dice 104-4/104-5 of a first tier on carrier 118, the plurality of dice of the first tier comprising a bridge die element 104-4);
arranging a plurality of the dice of the second tier on top of the dice of the first tier (Fig. 2A, arranging plurality of the dice 104-6/104-7 of the second tier on top of the dice of the first tier);
forming an integrated circuit die stack by connecting the dice of the first tier with the dice of the second tier, wherein the connecting comprises connecting the bridge die with at least two dice of the second tier (Fig. 2A, forming integrated circuit die stack by connecting the dice 104-4/104-5 of the first tier with the dice 104-6/104-7 of the second tier, the connecting comprises connecting the bridge die 104-4 with two dice 104-6 and 104-7 of the second tier); and
mounting the integrated circuit die stack die stack on a package substrate (Fig. 2A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (U.S. Patent Application Publication No. 2024/0395720), as applied to claims 1-3 above, in view of Then et al. (U.S. Patent Application Publication No. 2022/0399324).
Regarding to claim 4, Yim is silent as to pitch size of the hybrid bond. Then discloses a pitch of the hybrid bonds is less than 10 μm ([0044], lines 11-12). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yim in view of Then to configure a pitch of the hybrid bonds to be less than 10 μm in order to increase density of the bonds.
Regarding to claim 5, Yim teaches the routing connections are defined by a redistribution layer (RDL) formed on a substrate (Fig. 1, [0036], lines 9-13).
Regarding to claim 7, Yim teaches the bridge die comprises a plurality of through silicon vias (Fig. 1, element 197, [0063], lines 1-2).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (U.S. Patent Application Publication No. 2024/0395720), as applied to claim 1 above, in view of Verhaverbeke et al. (U.S. Patent Application Publication No. 2023/0148220).
Regarding to claim 10, Yim does not disclose a filler die disposed in a third tier of the integrated circuit die stack, the filler die not electrically connected to the second plurality of integrated circuit dies in the second tier. Verhaverbeke discloses a filler die disposed in a third tier of the integrated circuit die stack, the filler die not electrically connected to the second plurality of integrated circuit dies in the second tier (Fig. 23B, element 2360). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yim in view of Verhaverbeke to dispose a filler die in a third tier of the integrated circuit die stack, the filler die not electrically connected to the second plurality of integrated circuit dies in the second tier, in order to provide protection to the dice.
Regarding to claim 11, Verhaverbeke discloses a stiffener surrounding the integrated circuit die stack (Fig. 23B, element 2350), and a cover coupled to the stiffener and the filler die (Fig. 23B, element 2330).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (U.S. Patent Application Publication No. 2024/0395720), as applied to claims 12-14 above, in view of Then et al. (U.S. Patent Application Publication No. 2022/0399324).
Regarding to claim 15, Yim is silent as to pitch size of the hybrid bond. Then discloses a pitch of the hybrid bonds is less than 10 μm ([0044], lines 11-12). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yim in view of Then to configure a pitch of the hybrid bonds to be less than 10 μm in order to increase density of the bonds.
Regarding to claim 16, Yim teaches the routing connections are defined by a redistribution layer (RDL) formed on a substrate (Fig. 1, [0036], last 6 lines).
Pertinent Art
For the benefits of the Applicant, US-20250006644-A1, US-12399334-B2, US-20150112204-A1, US-20250140743-A1, US-20240395719-A1, US-12394682-B2, are cited on the record as being pertinent to significant disclosure the limitations of the independent claims of the defined invention, however, they do not disclose the limitations of some dependent claims. In particular, they do not disclose a stiffener surrounding the integrated circuit die stack, and a cover coupled to the stiffener and the filler die.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897