CTNF 18/518,196 CTNF 81344 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 40 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 40, it is unclear what is meant by the phrase “the CMOS transistor of the plurality of CMOS transistors”. The claim 40 depends upon already places a PUF device in direct contact with one of the CMOS transistors of the plurality, is “the CMOS transistor” the same as disclosed in claim 39, if so this is not a further limiting claim. If “the CMOS transistor” is a different CMOS transistor then “the CMOS transistor” lacks antecedent basis. Claims 40 has not been rejected over the prior art because, in light of the 35 U.S.C. 112 rejections supra, there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claims; hence, it would not be proper to reject the claims on the basis of prior art. As stated in In re Steele , 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 14, 15, and 35-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roest et al. (US Pat. Pub. 2011/0254141) in view of Kang et al (KR101566949B1) . Regarding claim 14, Roest teaches array comprising : a plurality of complementary metal-oxide-semiconductor (CMOS) transistors [paragraph [0042] teaches plurality of components such as an FRAM structure, memory devices such as ferroelectric ram (FRAM) have CMOS transistors associated with it, therefore Roest teaches a plurality of CMOS transistors in layer 5]; and a plurality of PUF devices each comprising a first electrode [fig. 2, 30’ corresponding to c1, c2, c3 and c4], a second electrode [fig. 2, 20], and a layer of silicon oxide positioned directly between the first copper electrode and the second electrode [fig. 2, 27 between 20 and 30, paragraph [0048] teaches silicon oxide]; wherein the plurality of PUF devices are positioned above the plurality of CMOS transistors [20, 27 and 30’ are positioned above 5, putting them above the CMOS devices in 5]. Roest fails to teach the first electrode is made of copper and instead teaches metals such as platinum or titanium, However, Kang teaches a PUF device in which one of the electrodes is copper as an alternative to other metals such as platinum or titanium [provided translation, paragraph [0034]]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Kang into the method of Roest by forming the first electrode from copper. The ordinary artisan would have been motivated to modify Roest in the manner set forth above for at least the purpose of utilizing known materials to ensure successful device fabrication. Furthermore, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07. Regarding claim 15, Roest in view of Kang discloses an integrated circuit comprising the array of claim 14 [Roest, paragraph [0042] teaches the components in layer 5 form an in electronic circuit, also a memory device is an integrated circuit]. Regarding claim 35, Roest in view of Kang teaches the array of claim 14, wherein the second electrode of one of the PUF devices comprises W, Ni, Pt, TiN, TaN, TiW, silicon, or polycrystalline silicon [Roest, paragraph [0043], Pt, Ni, W, Si]. Regarding claim 36, Roest in view of Kang discloses the array of claim 14, wherein one of PUF devices comprises an insulating layer positioned directly between the first electrode or the second electrode and a circuit [Roest, fig. 2, paragraph [0042] teaches layer 5 is silicon oxide, 5 contains the circuit and the silicon oxide would be between 20 and the circuit]. Regarding claim 37, Roest in view of Kang teaches the array of claim 36, wherein the insulating layer comprises SiO2, SiN or a polymer [Roest, paragraph [0042] silicon oxide]. Regarding claim 38, Roest in view of Kang discloses a switching voltage requires less than or equal to 3V [Kang, paragraph [0011], set voltage 2V is less than 3V]. Roest in view of Kang fails to specifically teach any amperage or time for the switching operation. However, the structure as taught by Roest in view of Kang is the same as claimed and has the same materials utilized in the same manner as instantly claimed. It would be obvious that the structure can be operated with a current less than or equal to 100uA for less than or equal to 400us, and thus Roest in view of Kang anticipates the limitations of this claim ( In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997)). Regarding claim 39, Roes in view of Kang teaches the array of claim 14, wherein each one of the PUF devices in direct contact with one of the plurality of CMOS transistors [fig. 2, c1, c2, c3, and c4 are in direct electrical contact with the circuit in layer 5] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 41-44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN M PARKER/Examiner, Art Unit 2899 Application/Control Number: 18/518,196 Page 2 Art Unit: 2899 Application/Control Number: 18/518,196 Page 3 Art Unit: 2899 Application/Control Number: 18/518,196 Page 4 Art Unit: 2899 Application/Control Number: 18/518,196 Page 5 Art Unit: 2899 Application/Control Number: 18/518,196 Page 6 Art Unit: 2899 Application/Control Number: 18/518,196 Page 7 Art Unit: 2899