DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guha et al. (2012/0214285).
Re claim 1, Guha teaches a three-dimensional (3D) memory device (Figs. 9-10), comprising: a vertical transistor (16), a capacitor (18), and a connect structure (22), wherein the capacitor (18) is coupled to the vertical transistor (16) through the connect structure (22), the connect structure (22) comprises a first interface (“top interface”) and a second interface (“bottom interface”), the first interface (“top interface”) is coupled to the capacitor (18), the second interface (“bottom interface”) is coupled to the vertical transistor (16), and a size of the first interface (“top interface”) is smaller (Fig. 9) than a size of the second interface (“bottom interface”).
Re claim 2, Guha teaches the 3D memory device of claim 1, wherein a shape of a cross-section of the connect structure (22) along a first direction is a rectangle (Fig. 10).
Re claim 3, Guha teaches the 3D memory device of claim 1, wherein the vertical transistor (16) comprises a semiconductor body (26) and a gate structure (32), the semiconductor body (26) extends in a same direction as the vertical transistor (16), and the gate structure (32) is in contact with one or more sides [35] of the semiconductor body (26).
Re claim 4, Guha teaches the 3D memory device of claim 3, wherein two ends of the semiconductor body (26) extend beyond the gate structure, respectively [35-40].
Re claim 5, Guha teaches the 3D memory device of claim 3, wherein the vertical transistor is a gate-all-around (GAA) transistor in which the gate structure fully circumscribes the semiconductor body in a plan view [40].
Re claim 6, Guha teaches the 3D memory device of claim 1, wherein a bit line (30a, 30b) and the capacitor (18) are coupled to opposite ends (Fig. 9) of the vertical transistor (16). Re claim 8, Guha teaches the 3D memory device of claim 1, wherein a dielectric medium (35) is filled between neighboring connect structures in the 3D memory device (Fig. 9).
Claim(s) 10-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guha et al. (2012/0214285).
Re claim 10, Guha teaches a method (Figs. 1-10), comprising: forming a first structure comprising a plurality of vertical transistors (16); forming a connect layer [25-34] over the first structure (Figs. 1-10); etching the connect layer to form [25-34] connect structures (Figs. 2-8), wherein each of the connect structures (22) is coupled to a corresponding one of the vertical transistors (16); and forming a plurality of capacitors (18) over the connect layer [25-34], wherein each of the plurality of capacitors (18) is coupled to a respective connect structure (22).
Re claim 11, Guha teaches the method of claim 10, wherein etching the connect layer comprises: etching a plurality of holes (60) through the connect layer [25-34]; and filling the plurality of holes with a dielectric medium (35).
Re claim 12, Guha teaches the method of claim 10, wherein etching the connect layer to form the connect structures comprises: etching through the connect layer along a first direction [24-34]; and etching through the connect layer along a second direction to form the connect structures [24-34], wherein the first direction is perpendicular to the second direction [24-34]. Re claim 14, Guha teaches the method of claim 10, wherein the method further comprises forming a bit line (30a, 30b) coupled to one or more of the plurality of vertical transistors (16). Claim(s) 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guha et al. (2012/0214285).
Re claim 16, Guha teaches a memory system ([36-39], Figs. 9-10), comprising: a three-dimensional (3D) memory device (Figs. 9-10), comprising: a vertical transistor (16), a capacitor (18), and a connect structure (22), wherein the capacitor (18) is coupled to the vertical transistor (16) through the connect structure (22), the connect structure (22) comprises a first interface (“top interface”) and a second interface (“bottom interface”), the first interface (“top interface”) is coupled to the capacitor (18), the second interface (“bottom interface”) is coupled to the vertical transistor (16), and a size of the first interface (“top interface”) is smaller (Fig. 9) than a size of the second interface (“bottom interface”); and a memory controller ([36-37]) coupled to the 3D memory device (Figs. 9-10) and configured to initiate operations of the 3D memory device (“DRAM”, [37]).
Re claim 17, Guha teaches the memory system of claim 16, wherein a shape of a cross-section of the connect structure (22) along a first direction is a rectangle (Fig. 10).
Re claim 18, Guha teaches the memory system of claim 16, wherein the vertical transistor (16) comprises a semiconductor body (26) and a gate structure (32), the semiconductor body (26) extends in a same direction as the vertical transistor (16), and the gate structure (32) is in contact with one or more sides [35] of the semiconductor body (26). Re claim 20, Guha teaches the memory system of claim 16, wherein a bit line (30a, 30b) and the capacitor (18) are coupled to opposite ends (Fig. 9) of the vertical transistor (16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Guha et al. (2012/0214285) in view of the following reasons. Re claim 7, Guha teaches the 3D memory device of claim 1.
Guha does not explicitly teach wherein a shape of a cross-section of the connect structure along a second direction is a trapezoid.
However, Applicant has not shown wherein a shape of a cross-section of the connect structure along a second direction is a trapezoid has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the shape of the connect structure so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Re claim 9, Guha teaches the 3D memory device of claim 1. Guha does not explicitly teach wherein the connect structure comprises a tungsten layer. However, Applicant has not shown wherein the connect structure comprises a tungsten layer has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the material of the connect structure so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Guha et al. (2012/0214285) in view of the following reasons.
Re claim 19, Guha teaches the memory system of claim 16. Guha does not explicitly teach wherein a shape of a cross-section of the connect structure along a second direction is a trapezoid.
However, Applicant has not shown wherein a shape of a cross-section of the connect structure along a second direction is a trapezoid has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the shape of the connect structure so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 13, Guha teaches the method of claim 10, yet remains explicitly silent to wherein the connect layer comprises a polysilicon layer, a silicide layer, and a tungsten layer.
Re claim 15, Guha teaches the method of claim 10, yet remains explicitly silent to wherein forming the connect layer over the first structure comprises: forming a polysilicon layer over the first structure; and forming a silicide layer over the polysilicon layer, wherein the connect layer comprises the polysilicon layer and the silicide layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897