DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A in the reply filed on 07/06/2026 is acknowledged. Claims 10-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, Species B and C.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2023 and 06/15/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Worley et al. [US 6,147,857 A], “Worley”.
Regarding claim 1, Worley discloses a semiconductor device (Fig. 1 -also see annotated Fig. 1* for clarity) including:
a substrate (123) having a first main surface and a second main surface (as shown);
a plurality of elements (112/113) formed on the first main surface of the substrate or above the first main surface (as shown);
at least one first power supply line (102) electrically connected to at least one of the plurality of elements (the first power supply line (102) is connected to elements (113) through 121), disposed in a first layer (the first layer is the layer with power supply line (102): “1stlayer”) provided above the first main surface of the substrate (as show in Fig.1), and having an upper surface, a first side surface continuously formed from the upper surface, and a second side surface that is opposite to the first side surface and continuously formed from the upper surface (as shown with power line (102)); and
at least one second power supply line (100: Col. 3, line 10-20: the plate 100 is connected to Vss) disposed in the first layer (1stlayer) and a second layer (the second layer is the metal layer (100) above power supply line (102): “2ndlayer”) above the first layer and disposed from the second layer to the first layer to cover the upper surface, the first side surface, and the second side surface in a part of the at least one first power supply line (as shown in Fig. 1).
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Regarding claim 2, Worley discloses claim 1, Worley discloses at least two signal lines (Fig 1*, 2SL) electrically connected to at least one of the plurality of elements (112)and disposed in at least the first layer (as shown).
Regarding claim 3, Worley discloses claim 2, Worley discloses the at least two signal lines are disposed from the second layer to the first layer ( the at least two signal lines goes from the bottom of the second layer to the top of the first layer) .
Regarding claim 4, Worley discloses claim 2, Worley discloses a first dielectric film (Fig. 1, 125, Col. 4 Line -13 teaches oxide) disposed between the at least two signal lines in the first layer (as shown) and having a first dielectric constant; and a second dielectric film (101: Col. 3 Lines 8-12 teaches silicon nitride) disposed between the at least one first power supply line and the at least one second power supply line in the first layer (as shown) and having a second dielectric constant higher than the first dielectric constant (SiN has a higher dielectric constant is higher than oxide).
Regarding claim 5, Worley discloses claim 2, Worley discloses in the first layer (1Stlayer), a distance between the at least two signal lines (2SL) is greater than a distance between the at least one first power supply line (102) and the at least one second power supply line (100) (as shown in Fig. 1*).
Regarding claim 7, Worley discloses claim 2, Worley discloses the at least one first power supply line (102) and the at least one second power supply line (100) are disposed to intersect each other in a plan view of the first main surface (as shown in Fig. 1).
Regarding claim 9, Worley discloses claim 1, Worley discloses the second power supply line is a ground line (100: Col. 3, line 10-20: the plate 100 is connected to Vss).
.Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Worley et al. [US 6,147,857 A], “Worley” as applied to claim 2 above, and further in view of Xie et al. [US 2023/0260892 A1], “Xie”.
Regarding claim 8, Worley discloses claim 2, Worley discloses does not explicitly disclose a cross-sectional area of the at least one first power supply line is greater than a cross- sectional area of each of the at least two signal lines.
However, Xie discloses semiconductor structure including a metal layer including a Vdd metal line, a Vss metal line, signal lines. Xie discloses a cross-sectional area of the at least one first power supply line (Fig. 5, 130) is greater than a cross- sectional area of each of the at least two signal lines (134).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of the at least two signal lines as taught in Xie in the device of Worley such that a cross-sectional area of the at least one first power supply line is greater than a cross- sectional area of each of the at least two signal lines because such a modification would allow for decoupling capacitance which decreases power supply noise within the device (¶[0018] of Xie). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
With the combination of claim 1 and 2, claim 6 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lanzillo et al [US 2022/0406717 A1] teaches a semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
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