DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1 and 9 have been amended.
Rejections under 35 USC 112
Previous 112 rejections for Claim(s) 1-10 are now withdrawn as amendments made to claim(s) 1 and 9 have overcome the previous 112 rejections.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 12/12/2025 with respect to Claim(s) 1-10 have been fully considered but they are not persuasive.
Applicant's arguments with respect to Claim(s) 1-10 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-10 herein.
Claim Objections
Claim(s) 1 and 9 are objected to because of the following informalities:
Claim(s) 1 and 9 recite a term “an stopped state” in paragraphs 6 and 4, respectively. The Examiner suggests amending the term to recite “a stopped state” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Waters et al. (US 20170139467; hereinafter Waters) in view of TAYA et al. (US 20090128714).
Regarding claim 1, Waters teaches in figure(s) 1-3 a connection control circuit conforming to the USB (Universal Serial Bus) Type-C standard (para. 11 - USB-C), the connection control circuit comprising:
a CC terminal (CC; fig. 1);
an operation mode detection circuit (mode control 130) configured to detect an operation mode (power mode 1, power mode 2wake1, wake2, wake3; figs. 1,3) of a first device (para. 11 - processor 110 with one or more USB devices) based on a voltage of a first node connected to the CC terminal (@144,150);
a receiver circuit (144,148,150) connected in parallel to the operation mode detection circuit and configured to receive the voltage of the first node (para. 33 - CC control circuit 44 of both ports is coupled through switches 46 for detecting a voltage generated at the connected CC pin and determining that a connection to a compatible device has been established);
a voltage change detection circuit (@144,148,150) configured to detect a change in a voltage level output from the receiver circuit (para. 19 - a comparator output indicating that the CC voltage has exceeded the threshold); and
an operation state control circuit (state machine 140) configured to control operation states of the operation mode detection circuit (130) and the receiver circuit according to a detection result of the voltage change detection circuit (144,148,150),
wherein, in a first state in which a second device (102 ) is not connected (port connection == no step 320; fig. 3B) to the first device (110), the operation state control circuit is configured to set the receiver circuit to the operating state (low power operation 312 in fig 3B) and set the operation mode detection circuit to the stopped state (para. 20 - low power mode operation in the unattached SRC state 201), wherein, in a second state in which the second device is connected to the first device (detected I2C connectivity step 322) and the voltage change detection circuit has detected a change in the voltage level output from the receiver circuit (@148 in fig. 1), the operation state control circuit is configured to set the receiver circuit to the stopped state (step 324 == No; fig. 3B ) and set the operation mode detection circuit to the operating state (LP power mode 2), and
wherein, in the second state, the operation mode detection circuit (130) is configured to detect the operation mode (LP mode) of the first device based on the voltage of the first node (voltage @ CC).
Waters does not teach explicitly control the operation mode detection circuit and the receiver circuit between an operating state and a stopped state.
However, TAYA teaches in figure(s) 1-14 control the operation mode detection circuit (28/14; fig. 1) and the receiver circuit (22/12) between an operating state (S3 state; fig. 4) and a stopped state (S1 state).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Waters by having control the operation mode detection circuit and the receiver circuit between an operating state and a stopped state as taught by TAYA in order to provide interruptible operation feature. It would have been a use of known technique to improve similar devices (methods, or products) in the same way as evidenced by "a control signal transmitted from the remote control unit and received by the wireless receiving circuit, and a preliminary activation circuit for starting electric power supply to the digital signal processing circuit to thereby activate the digital signal processing circuit when a pre-operation state where the remote control unit is expected to be operated during stoppage of electric power supply to the core circuit has occurred" (abstract).
Regarding claim 2, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 1, wherein the operation mode detection circuit comprises: a comparator (144,148,150) configured to compare the voltage of the first node and a predetermined reference voltage (Vth1..3); and a state machine (140) configured to determine the operation mode (power mode 1, power mode 2) of the first device according to an output of the comparator.
Regarding claim 3, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 1, wherein the operation mode detection circuit comprises: a plurality of comparators (144,148,150) each configured to compare a set predetermined reference voltage and the voltage of the first node; a state machine configured to determine the operation mode of the first device according to an output of the plurality of comparators; and a reference voltage generation circuit configured to generate respective reference voltages (Vth1…3 ), and supply each of the respective reference voltages to each of the plurality of comparators.
Regarding claim 4, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 2,
further comprising a first switching circuit (switches S3,S4) capable of switching between a state in which the first node is connected to a power supply potential via a pull-up resistor (RP1), and a state in which the first node is connected to a ground potential via a pull-down resistor (RD1).
Regarding claim 5, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 4, wherein, if the first device operates as a source (source port mode 304; fig. 3A), the first switching circuit is configured to set the state in which the first node is connected to the power supply potential via the pull-up resistor (RP1), and wherein, if the first device operates as a sink (sink port mode 306), the first switching circuit is configured to set the state in which the first node is connected to the ground potential via the pull-down resistor (RD1).
Regarding claim 6, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 4, wherein the CC terminal includes a CC1 terminal and a CC2 terminal (CC1, CC2; fig. 1), and wherein the pull-up resistor, the pull-down resistor, the first switching circuit, the comparator, and the receiver circuit are each provided so as to correspond to each of the CC1 terminal and the CC2 terminal.
Regarding claim 7, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 1, wherein the operation mode detection circuit and the receiver circuit are built in the same chip (USB port controller IC 120-1; fig. 1).
Regarding claim 8, Waters teaches in figure(s) 1-3 the connection control circuit according to claim 1, wherein the receiver circuit is configured using a single-end receiver built in a transceiver circuit conforming to the USB 2.0 standard (para. 11 - USB controller 120 in one example includes a terminal to electrically couple a baseband transceiver 124 with a configuration channel line 114 of the USB cable connector 102), and wherein an input of the single-end receiver is provided with a second switching circuit capable of switching between a state in which the first node is connected (para. 11 - baseband transceiver 124 includes an I/O connection to transmit data to the CC line 114 according to a transmit data signal from the host processor 110) and a state in which a USB bus terminal is connected (para. 11 - The controller IC 120 also includes a power circuit 122 connected to a bus voltage line 112 (VBUS) of the USB connector 102 via an output terminal OUT of the IC 120).
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over KO et al. (US 20190079130; hereinafter KO) in view of TAYA.
Regarding claim 9, KO teaches in figure(s) 1-14 a connection control method using a connection control circuit (100; fig. 1) conforming to the USB (Universal Serial Bus) Type-C standard (USB 110), the connection control circuit comprising: an operation mode detection circuit (130; fig. 1) configured to detect an operation mode (para. 29 - detection signal DET indicating that the low impedance is detected) of a first device (100) based on a voltage of a first node connected to a CC terminal (CC1,CC2); and a receiver circuit (140,150) connected in parallel to the operation mode detection circuit and configured to receive the voltage of the first node (para. 29 - detection signal DET may be provided to the main controller 150 and/or the power circuit 140), wherein the connection control method includes steps in which:
in a first state (S10; fig. 13) in which a second device (200; figs. 3) is not connected to the first device, the receiver circuit is set to an operating state and the operation mode detection circuit is set to a stopped state (para. 90 - When the USB device is set to the DFP, the CC pins (e.g., the CC1 pin A5 and the CC2 pin B5) may be pulled up);
in a second state (S20’) in which a second device is connected to the first device and a change in a voltage level output from the receiver circuit has been detected (para. 91 - the voltage of the CC pin may be changed according to the impedance with respect to the ground, and the impedance between the ground and the CC pin may be detected by measuring the voltage of the CC pin (or a voltage proportional to the voltage of the CC pin)), the receiver circuit is set to a stopped state and the operation mode detection circuit is set to an operating state; and
in the second state, the operation mode detection circuit detects the operation mode of the first device based on the voltage of the first node, and sets the first device to operate as a source or a sink (para. 90 - USB device supports a dual role port (DRP) capable of switching between a source (or host) and a sink (or device), the USB device may be set to a DFP or an upload faced port (UFP)) according to the detected operation mode (para. 91 - In operation S30, the DFP may be released. Because the detection of the impedance is completed in operation S20′).
Ko does not teach explicitly wherein the operation mode detection circuit and the receiver circuit are set to an operating state or a stopped state.
However, TAYA teaches in figure(s) 1-14 wherein the operation mode detection circuit (28/14; fig. 1) and the receiver circuit (22/12) are set to an operating state (S3 state; fig. 4) or a stopped state (S1 state).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ko by having wherein the operation mode detection circuit and the receiver circuit are set to an operating state or a stopped state as taught by TAYA in order to provide interruptible operation feature. It would have been a use of known technique to improve similar devices (methods, or products) in the same way as evidenced by "a control signal transmitted from the remote control unit and received by the wireless receiving circuit, and a preliminary activation circuit for starting electric power supply to the digital signal processing circuit to thereby activate the digital signal processing circuit when a pre-operation state where the remote control unit is expected to be operated during stoppage of electric power supply to the core circuit has occurred" (abstract).
Regarding claim 10, KO teaches in figure(s) 1-14 the connection control method according to claim 9, wherein, in the second state, the operation mode detection circuit compares a set predetermined reference voltage (V_REF; fig. 9) and the voltage of the first node, and determines the operation mode of the first device according to a result of the comparison (DET; para. 31 - power circuit 140 may mitigate or prevent an overcurrent from being supplied from the power source voltage by turning off at least one switch in response to the activated detection signal DET and/or under the control of the main controller 150).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858