Prosecution Insights
Last updated: July 17, 2026
Application No. 18/518,345

STACKED ELECTRONIC PACKAGES

Non-Final OA §102§103§112
Filed
Nov 22, 2023
Examiner
MOJADDEDI, OMAR F
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
469 granted / 525 resolved
+21.3% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
42 currently pending
Career history
562
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
85.8%
+45.8% vs TC avg
§102
8.2%
-31.8% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 525 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions 1. Applicant's election, without traverse, of claims 1-10 in the “Response to Restriction Requirement” filed on 03/13/2026 is acknowledged and entered by the Examiner. This office action consider claims 1-20 pending for prosecution, wherein claims 11-20 are withdrawn from further consideration, and claims 1-10 are presented for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 2. Claims 5-6 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 5, the instant claim recites limitations in view of the parent device claim 1, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “further comprising: a thermally-conductive heat sink formed within the first circuit substrate that extends from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate” (Claim 5; emphasis added). The claim is indefinite because of the following: i) The claim is indefinite because “further comprising: a thermally-conductive heat sink formed within the first circuit substrate that extends from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate” (Claim 5) is ambiguous and unclear. The limitation of “wherein the first electronic component disposed on the top surface of the first circuit substrate” adds confusion as the first electronic component was not claimed to be disposed on the top surface of the first circuit substrate in parent claim 1. Rather, a first electronic component was claimed to be mechanically bonded and electrically coupled to the top surface of the first circuit substrate or to the bottom surface of the second circuit substrate in claim 1. The limitation in claim wherein the first electronic component disposed on the top surface of the first circuit substrate in claim 5 defines a different location for the first electronic component, and has added confusion to the claim. Therefore, the limitation of “further comprising: a thermally-conductive heat sink formed within the first circuit substrate that extends from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate” (Claim 5) is indefinite and unclear. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Regarding Claim 6, it is rejected under 112(b) because of its dependency status from claim 5. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 3. Claims 1-6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Longo et al. (US 7550857 B1; hereinafter Longo). Regarding claim 1, Longo teaches an assembly (see the entire document, specifically Fig. 1+; C2 L9+, and as cited below) comprising: a first circuit substrate (514A; Fig. 5; C6 L57-67) having a top surface and bottom surface; a second circuit substrate (514B; Fig. 5; C6 L57-67) having a top surface and bottom surface, wherein the second circuit substrate (514B; Fig. 5; C6 L57-67) is disposed above the first circuit substrate (514A; Fig. 5; C6 L57-67) and the bottom surface of the second circuit substrate (514B; Fig. 5; C6 L57-67) faces the top surface of the first circuit substrate (514A; Fig. 5; C6 L57-67); a first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) disposed between the first circuit substrate (514A; Fig. 5; C6 L57-67) and the second circuit substrate (514B; Fig. 5; C6 L57-67)) that mechanically couples the first circuit substrate (514A; Fig. 5; C6 L57-67) to the second circuit substrate (514B; Fig. 5; C6 L57-67); wherein a first electronic component (518A; Fig. 5; C7 L1-25) is mechanically bonded and electrically coupled to the top surface of the first circuit substrate (514A; Fig. 5; C6 L57-67) or to the bottom surface of the second circuit substrate (514B; Fig. 5; C6 L57-67); and wherein the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer), the top surface of the first circuit substrate (514A; Fig. 5; C6 L57-67), and the bottom surface of the second circuit substrate (514B; Fig. 5; C6 L57-67) jointly define a cavity (area in the middle of Fig. 5 between upper surface 514U of 514A and lower surface 520L of 514B) between the first circuit substrate (514A; Fig. 5; C6 L57-67) and the second circuit substrate (514B; Fig. 5; C6 L57-67). Regarding claim 2, Longo teaches all of the features of claim 1. Longo further teaches wherein the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) includes an electrical interconnect ({538B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer)that electrically couples the first circuit substrate (514A; Fig. 5; C6 L57-67) to the second circuit substrate (514B; Fig. 5; C6 L57-67). Regarding claim 3, Longo teaches all of the features of claim 2. Longo further comprising: an electrically-conductive shield structure configured to shield the first electronic component (518A; Fig. 5; C7 L1-25) from electromagnetic interference or to shield components outside the electrically-conductive shield structure from electromagnetic interference generated within the shield structure; wherein the shield structure is formed at least in part by a first portion disposed on or within the first circuit substrate and a second portion disposed on or within the second circuit substrate; and wherein the first portion of the shield structure is directly electrically coupled to the second portion of the shield structure by the electrical interconnect of the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer). Regarding claim 4, Longo teaches all of the features of claim 1. Longo further comprising: a third circuit substrate (514C; Fig. 5; C6 L57-67) having a top surface and bottom surface, wherein the third circuit substrate (514C; Fig. 5; C6 L57-67) is disposed above the second circuit substrate (514B; Fig. 5; C6 L57-67) and the bottom surface of the third circuit substrate (514C; Fig. 5; C6 L57-67) faces the top surface of the second circuit substrate; and a second interposer substrate ({538C, 540C}; Fig. 5; C8 L1-33; where 538C and portions of 540C that encompass 538C are construed to be an interposer) disposed between the second circuit substrate (514B; Fig. 5; C6 L57-67) and the third circuit substrate (514C; Fig. 5; C6 L57-67) that mechanically couples the third circuit substrate (514C; Fig. 5; C6 L57-67) to the second circuit substrate (514B; Fig. 5; C6 L57-67) wherein the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) includes and electrical interconnect ({538B}; Fig. 5; C7 L55-63)that couples the first circuit substrate (514A; Fig. 5; C6 L57-67) to the second circuit substrate (514B; Fig. 5; C6 L57-67); wherein the second interposer substrate ({538C, 540C}; Fig. 5; C8 L1-33; where 538C and portions of 540C that encompass 538C are construed to be an interposer) includes an electrical interconnect ({538C}; Fig. 5; C8 L1-33) that couples the second circuit substrate (514B; Fig. 5; C6 L57-67) to the third circuit substrate (514C; Fig. 5; C6 L57-67); and wherein the first circuit substrate (514A; Fig. 5; C6 L57-67) is electrically coupled to the third circuit substrate (514C; Fig. 5; C6 L57-67) via the electrical interconnects ({538B}; Fig. 5; C7 L55-63) of the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) and the second interposer substrate. Regarding claim 5, Longo teaches all of the features of claim 1. Longo further comprising: a thermally-conductive heat sink formed within the first circuit substrate that extends from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate (see section 2, above; 112(b) rejection). Regarding claim 6, Longo teaches all of the features of claim 5. Longo further comprising: a first set of electrical contacts that are disposed on a circuit substrate that is spaced apart from the first circuit substrate; wherein the first set of electrical contacts includes electrical contacts that are coupled to one or more electronic components within the assembly (see section 2, above; 112(b) rejection). Regarding claim 8, Longo teaches all of the features of claim 1. Longo further teaches wherein the first electronic component (518A; Fig. 5; C7 L1-25) is mechanically bonded and electrically coupled to the top surface of the first circuit substrate (514A; Fig. 5; C6 L57-67); and wherein a second electronic component (5188; Fig. 5; C7 L1-25) is mechanically bonded and electrically coupled to the bottom surface of the second circuit substrate (514B; Fig. 5; C6 L57-67). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 4. Claims 7 and 9-10 are rejected under 35 U.S.C.103 as being unpatentable over Longo et al. (US 7550857 B1; hereinafter Longo), in view of the following statement(s). Regarding claim 7, Longo teaches all of the features of claim 1. Longo further teaches wherein the first circuit substrate (514A; Fig. 5; C6 L57-67) is coupled to the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) via a metal pin ({538B}; Fig. 5; C7 L34-38; where 538 is solder, electrically conductive adhesive, or other electrically conductive material) that is mated with a corresponding socket (see Fig. 5; where 38B protrudes from 514A and into 540B); wherein the metal pin ( ({538B}; Fig. 5; C7 L34-38; where 538 is solder, electrically conductive adhesive, or other electrically conductive material) protrudes from a surface of the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer) and the corresponding socket is a recessed socket formed in the first circuit substrate (514A; Fig. 5; C6 L57-67); or wherein the metal (see below for “pin”)( ({538B}; Fig. 5; C7 L34-38; where 538 is solder, electrically conductive adhesive, or other electrically conductive material) protrudes from a surface of the first circuit substrate (514A; Fig. 5; C6 L57-67) and the corresponding socket is a recessed socket (see Fig. 5; where 38B protrudes from 514A and into 540B) formed in the first interposer substrate ({538B, 540B}; Fig. 5; C7 L55-63; where 538B and portions of 540B that encompass 538B are construed to be an interposer). Furthermore, the Applicant has not presented persuasive evidence that the claimed “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” (emphasis added) is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate). Also, the Applicant has not shown that “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Instead, paragraph [0024] of the instant invention discloses other possible options such as “The interposers 150 can be bonded to the carriers 120 via solder bump bonding to contact pads (i.e., interconnects 115 at surfaces of the carriers 120), solder reflow, epoxy bonding, and/or any other suitable methods”. Therefore, no rationale is given that the invention will not function without “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate”. Thus, the claimed “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” is not critical to the invention. Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). PNG media_image1.png 18 19 media_image1.png Greyscale In view of the above, as there is no persuasive evidence that the particular configuration of “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” is significant. Thus, the claimed limitation of “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that is mated with a corresponding socket; wherein the metal pin protrudes from a surface of the first interposer substrate and the corresponding socket is a recessed socket formed in the first circuit substrate; or wherein the metal pin protrudes from a surface of the first circuit substrate and the corresponding socket is a recessed socket formed in the first interposer substrate” is not patentable over Longo. Regarding claim 9, Longo teaches all of the features of claim 1. Longo further teaches wherein the cavity is filled with a volume of (see below for “polymeric”) molding material (540B; Fig. 5; C7 L55-63). As noted above Longo does not expressly disclose wherein the cavity is filled with a volume of polymeric molding material, though it does teach that material 540 is an underfill material However, the instant specification contains no disclosure of either the critical nature of the claimed “wherein the cavity is filled with a volume of polymeric molding material” or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen compositions or upon another variable recited in a claim, the applicant must show that the chosen compositions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).). Regarding claim 10, Longo teaches all of the features of claim 1. Longo further teaches wherein an outer edge of the assembly (see Fig. 5) is encapsulated within a volume of (see below for “polymeric”) molding material (530; Fig. 5; C8 L19-19; see C5 L54-59). As noted above Longo does not expressly disclose wherein an outer edge of the assembly is encapsulated within a volume of polymeric molding material, though it does teach that encapsulating material (530; Fig. 5; C8 L19-19; see C5 L54-59) is an overmold. However, the instant specification contains no disclosure of either the critical nature of the claimed “wherein an outer edge of the assembly is encapsulated within a volume of polymeric molding material” or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen compositions or upon another variable recited in a claim, the applicant must show that the chosen compositions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OMAR F MOJADDEDI/Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 22, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 525 resolved cases by this examiner. Grant probability derived from career allowance rate.

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