DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-8, in the reply filed on January 15, 2026 is acknowledged.
Accordingly, claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 15, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 30, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US Pub 2021/0193672).
In re claim 1, Kim et al discloses a semiconductor device (i.e. see at least Figure 30), comprising: a semiconductor structure (i.e. see at least Figure 30) comprising a stack of conductive layers (i.e. 572, 574, 576) and isolating layers (i.e. 315) alternating with each other along a first direction (i.e. 1st direction), wherein the semiconductor structure comprises an array region (i.e. region I) and a connection region (i.e. region II) adjacent to the array region in a second direction (i.e. 2nd direction) perpendicular to the first direction; and contact structures (i.e. 622) extending through at least a part of the connection region along the first direction, wherein a conductive layer (i.e. 576) of the stack is coupled to a contact structure (i.e. 622 or 626) of the contact structures through a connection layer (i.e. 577) in the connection region, wherein the conductive layer (i.e. 576) is in contact with the connection layer (i.e. 577) along the second direction, and wherein a filling film (i.e. 560) is in a space between a portion of the conductive layer (i.e. 576) and at least one isolating layer (i.e. 315) adjacent to the conductive layer.
In re claim 3, Kim et al discloses wherein the connection layer comprises a conductive material, and the filling film comprises the conductive material (i.e. see at least paragraphs 0129, 0130, 0137).
In re claim 5, Kim et al discloses wherein the filling film is in contact with an end of the connection layer along the second direction, and wherein the end of the connection layer comprises a first surface in contact with the conductive layer and a second surface in contact with the filling film, the first surface and the second surface being offset along the second direction (i.e. see at least Figure 30).
In re claim 8, Kim et al discloses wherein the semiconductor structure comprises a plurality of dielectric layers (i.e. 460) and isolating layers (i.e. 315) alternating with each other along the first direction in the connection region, and wherein each of the contact structures (i.e. 622 or 626) extends through a respective set of dielectric layers and isolating layers in the connection region, and the connection layer (i.e. 577) is between two adjacent isolating layers in the connection region (i.e. see at least Figures 28 and 30).
Allowable Subject Matter
Claims 2, 4, 6, and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHONY HO/Primary Examiner, Art Unit 2817
Prosecution Insights