DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, and 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recited “pads of the semiconductor devices” (plural)
Only antecedent basis established by Claim 1 is “one or more pads located on a side surface of the at least one of the semiconductor devices”. Under broadest reasonable interpretation, it is unclear whether Claim 9 refers back to Claim 1 pads (limited to at least one device) or independently claims pads of the full plural class of devices.
For the purposes of examination, the Examiner will treat “pads of the semiconductor devices” as –the one or more pads of the at least one of the semiconductor devices--.
Claim 11 recites “the at least one of the semiconductor devices further comprises one or more wires routed through and isolated from the one or more sealing structures” using indefinite article rather than “the” before
Claim 1 already establishes antecedent basis for “one or more wires routed through the one or more sealing structures and coupled to the one or more pads”
Under ordinary claim construction “the at least one of the semiconductor devices further comprises one or more wires routed through and isolated from the one or more sealing structures” of Claim 11 this limitation reads as introducing a second, additional wire distinct from claim 1 wire, rather than as further characterizing the wire already claimed,
It is unclear whether claim 11 adds the “isolated from” property to the existing wire of Claim 1 or claims a structurally distinct second wire that unlike Claim 1 wire, is not required to be coupled to any pad.
For the purposes of examination the Examiner will treat “the at least one of the semiconductor devices further comprises one or more wires routed through and isolated from the one or more sealing structures” as – wherein the one or more wires are further isolated from the one or more sealing structures--
Claim 12 is rejected as being dependent on Claim 11
Claim 13 recites the limitation " the coupling structure comprises an interposer configured to horizontally interconnect the semiconductor devices and the substrate." in line 8. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, the Examiner will treat “the semiconductor devices and the substrate.” as -semiconductor devices and a substrate.
Claims 14, 15 are rejected as being dependent on Claim 13
Claim 15, unamended, recites that the coupling structure “comprises a circuit layer coupled to the first contacting structures and the second contacting structures”
Claim 13, as amended, recites “an internal circuit layer” with the first and second contacting structures each “coupled to the internal circuit layer”. Use of indefinite article “a circuit layer” rather than “ the internal circuit layer” renders it unclear whether Claim 15 refers to the same internal circuit layer (in which case Claim 15 adds nothing and improper under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends or claims a second, additional circuit layer for which the originally filed specification discloses no support.
For the purposes of examination, the Examiner will treat as “a circuit layer” as --the internal circuit layer—and Claim 15 as having the same scope as Claim 13.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 10 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 10 does not narrow the scope of Claim 1 in any respect. The sealing structure limitation it recites is identical to limitation already present in Claim 1 from which it depends.
Applicants may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8-15 s/are rejected under 35 U.S.C. 102(A1) as being anticipated by Cheah et al. (US 2013/0341803 A1).
Regarding Claim 1, Cheah (Fig. 2A-E) discloses a package structure, comprising
a substrate (246) and semiconductor devices (220/221; Semiconductor multi-die structures) stacked over the substrate (246), wherein
the semiconductor devices (220) are stacked along a first direction (vertically),
wherein
at least one of the semiconductor devices comprises one or more sealing structures (passivation layer 240) and one or more pads (die side pad structure 236) located on a side surface of the at least one of the semiconductor devices (120) (Fig. 2), and one or more wires (dies backside metal routing 238) routed through the one or more sealing structures (240) and coupled to the one or more pads. (236). (die backside metal routing 238 is “included in” passivation layer 240, and is disclosed for coupling (in conjunction with die side pad 236) to VSC interconnect 204 (i.e. routed through passivation layer to the pad)
Regarding Claim 2, Cheah (Fig. 2) discloses the package structure of claim 1, wherein
the semiconductor devices (220) are aligned along one side of the semiconductor devices. (aligned side surface facing VCS, See Fig. 2A, D, E)
Regarding Claim 3, Cheah (Fig. 2) discloses the package structure of claim 1, wherein
at least one of the semiconductor devices (220) comprises a side surface parallel to the first direction (Vertically), and one or more pads (236) of the at least one of the semiconductor devices are disposed on the side surface. (See Fig. 2). (the side surface of the stacked die pad 236 is vertical i.e. parallel to the z-axis stacking direction).
Regarding Claim 8, Cheah (Fig. 2) discloses the package structure of claim 1, wherein
the package structure further comprises a coupling structure (VCS 201, 202, 204, 272) parallel to the first direction (vertical), and
the coupling structure (201) is configured to couple semiconductor devices (220) and the substrate (246) (VSC 201 couples MSD 220 via front interconnections 204/202)
Regarding Claim 9, Cheah (Fig. 2) discloses the package structure of claim 8, wherein
the coupling structure (VCS 201) comprises contacting structures (204, 202, 272,274) coupled to pads (236) of the semiconductor devices (220) and the substrate (245).
Regarding Claim 10, Cheah (Fig. 2) discloses the package structure of claim 1, wherein
at least one of the semiconductor devices (220) comprises one or more sealing structures. (a passivation layer 240).
Regarding Claim 11, Cheah (Fig. 2) discloses the package structure of claim 10, wherein
the at least one of the semiconductor devices (220) further comprises one or more wires (DMB routing 238 included in passivation layer 240) routed through and isolated from the one or more sealing structures (a passivation layer 240).
The Examiner notes that as long as the one or more sealing structures is not conductive the limitation “isolated from the one or more sealing structures” is considered to be met.
Passivation layer 240 is a dielectric layer; a metal routing line embedded in the dielectric passivation layer is inherently isolated from that layer since the layer itself in non-conductive.
Regarding Claim 12, Cheah (Fig. 2) discloses the package structure of claim 11, wherein
the one or more wires (238) are coupled to the pads (236) of the at least one of the semiconductor devices (220).
Regarding Claim 13, Cheah (Fig. 2A-E) discloses a coupling structure, comprising:
an internal circuit layer (TSVs 270 of VSC 201);
first contacting structures (204, 202) on a first side surface of the coupling structure (disposed in the active side of VSC 201) coupled to the internal circuit layer (270); and
second contacting structures (die side pad structure 272) on a second side surface of the coupling structure (on the bottom edge of 201), wherein
the second side surface (bottom side) is perpendicular to the first side surface (vertical active face bearing 204), and wherein
the coupling structure comprises an interposer (201) configured to horizontally interconnect the semiconductor devices (220/221) and the substrate (246) (201 electrically couples MSD structures 220/221 via 270 and interconnected to substrate 246 via 272/274).
Regarding Claim 14, Cheah discloses the coupling structure of claim 13, wherein
the first contacting structures (204, 202) are coupled to semiconductor devices (220/221), and the second contacting structures (272/274) are coupled to a substrate (274).
Regarding Claim 15, Cheah discloses the coupling structure of claim 13, wherein
the coupling structure (270) comprises a circuit layer (270) coupled to the first contacting structures (204/202) and the second contacting structures (272/274) (Fig. 2) [0026].
Response to Arguments
Applicant's arguments filed 07/02/2026 concerning Claim 1-3 and 8-12 have been fully considered but they are not persuasive.
Regarding Applicant’s Arguments on page 7 concerning Claim 1 that
“The Office Action maps the claimed pads to the die side pad structure 136 of Cheah, maps the claimed wires to the die backside metal routing 138 of Cheah, and asserts that the wires 138 are "coupled to" the pads 136 (Office Action at p. 7). Cheah, however, does not disclose this arrangement.”
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The Examiner notes that Applicant’s traversal addressed only to the Fig. 1 of Cheah. Cheah discloses the identical structural relationship in Fig. 2 embodiment. The rejection is maintained in this independently anticipatory basis.
Cheah discloses “The die backside metal routing 260 may be included in a passivation layer 264 as part of a die backside metallization (DBM) layer 266, as is depicted in FIG. 2B.” [0024]
Fig. 2B depicts dies side pad 236, routing 238 and passivation layer 240. 236 and 238 both connected to the same exact contact. Thus, discloses to a POSITA that wire 238 is routed through passivation layer 240 to reach pad 236 identical to the relationship recited in Claim 1.
Applicant’s arguments with respect to claim(s) 13-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dabral et al. (Fig. 2A, 2B) discloses wires (130) routed through sealing structures (160).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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