DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of species i, figs. 1A-1B, claims 1-15, in the reply filed on 4/3/26 is acknowledged. The traversal is on the ground(s) that “However, Applicant traverses the restriction as presented as Applicant submits that the articulated Species I reads on at least Figs. IA- 1G”.
In response, it is acknowledged that Figs. 1C-1G belong with species A. However, elected species (i) is distinct from species (ii)-(v) because each of the species comprises different geometries of the contact region, emitter region, gate region and/or dummy portion.
The requirement is still deemed proper and is therefore made FINAL.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 4/3/26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito[1], US Publication No. 2019/0051739 A1.
Naito[1] anticipates:
1. A semiconductor device (see figs. 22a-22b and figs. 3a-3b) comprising a gate trench portion (40) and a first trench portion (30) adjacent to the gate trench portion, the semiconductor device comprising:
a drift region (18) of a first conductivity type (N-) provided in a semiconductor substrate;
a base region (14) of a second conductivity type (P-) provided above the drift region;
an emitter region (12) of the first conductivity type (N+) that is provided above the base region and has a higher doping concentration than that of the drift region; and
a contact region (15) of the second conductivity type (P+) that is provided above the base region and has a higher doping concentration than that of the base region, wherein
in a mesa portion (60) between the gate trench portion (40) and the first trench portion (30), the contact region has a first contact portion and a second contact portion (e.g. see first contact portion and second contact portion annotated in fig. 22a) that are provided to extend from the first trench portion (30) to below a lower end of the emitter region (12); and
the first contact portion is provided to extend further from the first trench portion
than the second contact portion in a trench array direction (e.g. see first contact portion and second contact portion annotated in fig. 22a). See Naito[1] at para. [0001] – [0224], figs. 1-22.
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2. The semiconductor device according to claim 1, wherein below the emitter region (12), the second contact portion (15 in fig. 22b) is positioned at a position closer to a center portion side of the emitter region (12) than the first contact portion (e.g. see first contact portion annotated in fig. 22a) in a trench extending direction, figs. 22a-22b.
3. The semiconductor device according to claim 1, wherein the first contact portion (e.g. see first contact portion annotated in fig. 22a) and the second contact portion (15 in fig. 22b) are in contact with the lower end of the emitter region (12), figs. 22a-22b.
Regarding claim 4:
Naito[1] teaches the limitations as applied to claim 3 above.
5. The semiconductor device according to claim 1, wherein in a center portion of the emitter region (12) in a trench extending direction, the lower end of the emitter region (12) is in contact with the base region (14), fig. 22b.
6. The semiconductor device according to claim 1, wherein
(see fig. 22a) below the emitter region (12), the first contact portion (e.g. see first contact portion annotated in fig. 22a) is in contact with the gate trench portion (40); and
(see fig. 22b) below the emitter region (12), the second contact portion (15 in fig. 22b) is spaced apart from the gate trench portion (40)
8. The semiconductor device according to claim 1, wherein a magnitude of a step in the trench array direction of the first contact portion (e.g. see first contact portion annotated in fig. 22a) and the second contact portion (15 in fig. 22b) is 10% or more and 50% or less of a mesa width of the mesa portion (60), figs. 22a-22b.
9. The semiconductor device according to claim 1, wherein the first contact portion (e.g. see first contact portion annotated in fig. 22a) and the second contact portion (15 in fig. 22b) are provided on a front surface of the semiconductor substrate at a sidewall of the first trench portion (30), figs. 22a-22b.
10. The semiconductor device according to claim 1, further comprising an interlayer dielectric film (38) provided above the semiconductor substrate, wherein the emitter region (12) is connected to an emitter electrode (52) via a contact hole (54) provided penetrating through the interlayer dielectric film, fig. 22b.
11. The semiconductor device according to claim 10, wherein the emitter region (12) extends beyond the contact hole (54) from the gate trench portion (40) in the trench array direction, figs. 22a-22b.
12. The semiconductor device according to claim 11, wherein the emitter region (12) extends from the gate trench portion (40) and terminates without reaching the first trench portion (30) in the trench array direction (e.g. Fig. 22a is along cross-section g-g in Fig. 22a. Along cross-section g-g, the emitter region terminates without reaching the first trench portion 30.)
13. The semiconductor device according to claim 11, wherein the second contact portion (15 in fig. 22b) extends beyond the contact hole (54) from the first trench portion (30) in the trench array direction (e.g. see fig. 22a, also see enlarged fig. 22b below showing this claim limitation).
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14. The semiconductor device according to claim 1, wherein the contact region has a third contact portion (e.g. see third contact portion annotated in fig. 22a) that is alternately provided with the emitter region (12) along a trench extending direction in a front surface of the semiconductor substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito[1], as applied to claim 1 above.
Regarding claim 7:
Naito[1] teaches all the limitations of claim 1 above, but is silent the second contact portion is spaced apart by 0.6 μm or more from the gate trench portion in the trench array direction.
However, it would have been obvious to one of ordinary skill in the art to form “the second contact portion is spaced apart by 0.6 μm or more from the gate trench portion in the trench array direction”, because Naito[1] teaches the claimed distance represented by Wed in fig. 1a is a result effective variable that can improve the latch-up resistance of the transistor. See Naito[1] at para. [0113].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito[1], as applied to claim 1 above, in view of Naito[2], US Publication No. 2018/0366578 A1.
Regarding claim 15:
Naito[1] teaches all the limitations of claim 1 above, but is silent wherein the first trench portion is a dummy trench portion set at an emitter potential.
In an analogous art, Naito[2] teaches (see fig. 22) wherein a first trench portion (34) is a dummy trench portion set at an emitter potential (E), para. [0131].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Naito[1] with the teachings of Naito[2] because “Holes are distributed continuously from the dummy trench portion 30 to the lower end of the gate trench portion 40. Due to this hole distribution, large displacement current flows to a region near the lower end of the gate trench portion 40 at the time of turn-on, in some cases.” See Naito[2] at para. [0131].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
3 June 2026
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