Prosecution Insights
Last updated: July 05, 2026
Application No. 18/518,568

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Non-Final OA §102§103
Filed
Nov 23, 2023
Priority
Dec 08, 2021 — JP 2021-199175 +1 more
Examiner
SYLVIA, CHRISTINA A
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
666 granted / 760 resolved
+19.6% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
22 currently pending
Career history
786
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.8%
+36.8% vs TC avg
§102
10.0%
-30.0% vs TC avg
§112
12.6%
-27.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 760 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 12/22/2023. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on 03/25/2026 is acknowledged. Claim 18 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/25/2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3,5-8,11,15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shirakawa et al. (PG Pub 2017/0141517; hereinafter Shirakawa). PNG media_image1.png 492 440 media_image1.png Greyscale Regarding claim 1, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a semiconductor apparatus having a MOS gate structure (see claim limitations below), comprising: a semiconductor substrate 13; a first interlayer dielectric film 8a provided above an upper surface of the semiconductor substrate and including a first opening (space separating adjacent 8a’s); and a second interlayer dielectric film 8b stacked on the first interlayer dielectric film and including a second opening (space separating adjacent 8b’s) overlapping the first opening in a top view (see Fig. 2c), wherein a width of the first opening (annotated “w1” in Fig. 2c above) in a first direction (horizontal) is different from a width of the second opening in the first direction (annotated “w2” in Fig. 2c above), at a boundary height (annotated “h1” in Fig. 2c above) between the first interlayer dielectric film and the second interlayer dielectric film (see Fig. 2c). Regarding claim 2, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches the width of the second opening (“w2”) in the first direction (horizontal) is larger than the width of the first opening (“w1”) in the first direction at the boundary height (h10) (w2>w1) (see Fig. 2c). Regarding claim 3, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches at least part of an upper surface (annotated “upper” in Fig. 2c above) of the first interlayer dielectric film 6a is not covered with the second interlayer dielectric film 6b (see Fig. 2c). Regarding claim 5, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a gate trench 7 portion provided from the upper surface of the semiconductor substrate (top of 13) to an inside of the semiconductor substrate (see Fig. 2c), wherein the gate trench portion includes: a gate conductive portion 7 provided on the semiconductor substrate; and a gate dielectric film 6 which insulates the gate conductive portion from the semiconductor substrate, and the first interlayer dielectric film 8a covers at least part of an upper surface of the gate conductive portion (see Fig. 2c). Regarding claim 6, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a plurality of gate trench portions (plurality of 7’s) including the gate trench portion (see Fig. 2c), wherein the plurality of gate trench portions are arranged in the first direction (in the horizontal direction; see Fig. 2c). Regarding claim 7, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a mesa portion (annotated “mesa” in Fig. 2c above) provided between the plurality of gate trench portions 7, wherein a thickness of the first interlayer dielectric film is equal to or less than a width of the mesa portion in the first direction (horizontal) (see Fig. 2c). Regarding claim 8, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches comprising a first plug metal 10 at least partially provided in the first opening (portion of 10 between 8a’s); and a second plug metal 10 at least partially provided in the second opening (portion of 10 between 8b’s). Regarding claim 11, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a thickness of the second interlayer dielectric film (annotated “t2”) is larger than a thickness of the first interlayer dielectric film (annotated “t1”) (t2>t1; see Fig. 2c). Regarding claim 15, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches comprising a plug metal 7 provided in the semiconductor substrate 13, below the first opening (see Fig. 2c). Regarding claim 19, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a gate trench portion 6,7 provided from the upper surface of the semiconductor substrate 13 to an inside of the semiconductor substrate (see Fig. 2c), wherein the gate trench portion includes: a gate conductive portion 7 provided on the semiconductor substrate; and a gate dielectric film 6 which insulates the gate conductive portion from the semiconductor substrate (see Fig. 2c), and the first interlayer dielectric film 6a covers at least part of an upper surface of the gate conductive portion (see Fig. 2c). Regarding claim 20, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a gate trench portion 6,7 provided from the upper surface of the semiconductor substrate 13 to an inside of the semiconductor substrate (see Fig. 2c), wherein the gate trench portion includes: a gate conductive portion 7 provided on the semiconductor substrate; and a gate dielectric film 6 which insulates the gate conductive portion from the semiconductor substrate (see Fig. 2c), and the first interlayer dielectric film 6a covers at least part of an upper surface of the gate conductive portion (see Fig. 2c). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 2. Claim 4 and claim 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shirakawa, as applied to claim 1 above. Regarding claim 4, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches the width of the second opening in the first direction is larger than the width of the first opening in the first direction at the boundary height. However, one of ordinary skill in the art would have found it obvious to change the width of the second opening relative to the first opening (e.g. to be smaller, equal to or greater than), to best satisfy the end desired function. Furthermore, according to MPEP § 2144(IV), where the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”). Regarding claim 10, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches a side wall (e.g. right sidewall) of the first opening (space between adjacent 8a’s) is equal to a side wall (e.g. right sidewall) of the second opening (space between adjacent 8a’s). However, one of ordinary skill in the art would have found it obvious to change the shape of the first sidewall relative to the second sidewall (e.g. to be smaller, equal to or greater than), to best satisfy the end desired function. Furthermore, according to MPEP § 2144(IV), where the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”). 3. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shirakawa, as applied to claim 8 above, and further in view of Kamibaba et al. (PG Pub 2019/0326424; hereinafter Kimibaba). Regarding claim 9, refer to the Examiner’s mark-up of Fig. 2c provided above, Shirakawa teaches the first plug metal 7 and the second plug metal 7 (see Fig. 2c). Shirakawa does not teach “a barrier metal provided between the first plug metal and the second plug metal and containing titanium.” PNG media_image2.png 490 480 media_image2.png Greyscale In the same field of endeavor, refer to Fig. 3-provided above, Kimibaba teaches a semiconductor device 101 comprising: a barrier metal 13 provided between the first plug metal 11 and the second plug metal 10 and containing titanium (para [0036]). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a barrier metal between the first plug metal and the second plug metal, as taught by Kimibaba, to reduce the contact resistance between the emitter layer and the diffusion layer (para [0036]). Allowable Subject Matter 4. Claims 12-14 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 12 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 12, an interval at which a plurality of first openings including the first opening are arranged in the first direction is different from an interval at which a plurality of second openings including the second opening are arranged in the first direction. Claims 13-14 would be allowable, because they depend on allowable claim 12. Claim 16 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 16, a plurality of gate trench portions provided from the upper surface of the semiconductor substrate to an inside of the semiconductor substrate; and a mesa portion provided between two of the gate trench portions and extending in a trench extending direction at the upper surface of the semiconductor substrate, wherein the plug metal includes: a first segment; and a second segment provided side by side with the first segment in the trench extending direction and having a width larger than that of the first segment, and at least part of the first segment of the plug metal is arranged at a position which does not overlap the second opening. Claim 17 would be allowable, because it depends on allowable claim 16. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Nov 23, 2023
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.4%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 760 resolved cases by this examiner. Grant probability derived from career allowance rate.

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