Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
In response to election/restriction, applicant elected claims 1-8 without traverse.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Barwicz et al. (US 2016/0252688, hereinafter Barwicz) in view of Akamatsu (JP 2002016211, hereinafter Akamatsu) and further in view of Nystrom et al. (US 2014/0178644, hereinafter Nystrom).
With respect to claim 1, Barwicz discloses a method for packaging a chip (Para 0003; and 0013), comprising: providing a carrier (102/110s of Fig. 1B), the carrier comprising a substrate (102) and a plurality of first pads (110-1…110-3) disposed on a surface of the substrate (Fig. 1B); forming a first solder (130) paste on each of the plurality of first pads (Fig. 1B); forming at least one positioning post (106-3 – Para 0018) on the surface of the substrate where the plurality of first pads is disposed (Fig. 1B); providing a chip (200 of Fig. 5A), the chip comprising a body (Fig. 5A ) and a plurality of second pads (210-3; 210-4) disposed on a surface of the body (Fig. 5A); and melting and solidifying the solder paste to form a solder ball (130 of Fig. 5C; Para 0045), which connects the chip to the carrier, thereby obtaining the chip packaging structure (Para 0011; 0015; 0032).
Barwicz does not explicitly disclose forming a second solder paste on each of the plurality of second pads; defining at least one groove on the surface of the body where the plurality of second pads is disposed; accommodating one of the at least one positioning post in a corresponding one of the at least one groove, melting and solidifying the first solder paste and the second solder paste causing the first solder paste to be connected to the second solder paste.
In an analogous art, Akamatsu discloses forming a second solder paste (3 of Fig. 1) on each of the plurality of second pads causing the first solder paste to be connected to the second solder paste (Fig. 3); melting and solidifying the first solder paste and the second solder paste causing the first solder paste to be connected to the second solder paste (Fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz’s device by having Akamatsu’s disclosure in order to create strong connections between different components.
Barwicz/Akamatsu does not explicitly disclose defining at least one groove on the surface of the body where the plurality of second pads is disposed; accommodating one of the at least one positioning post in a corresponding one of the at least one groove.
In an analogous art, Nystrom discloses defining at least one groove (92 of Fig. 9) on the surface of the body where the plurality of second pads is disposed (Fig. 9); accommodating one of the at least one positioning post (42 of Fig. 8) in a corresponding one of the at least one groove (Fig. 8-9).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu’s device by having Nystrom’s disclosure in order to improve the alignments of different components of a semiconductor device.
With respect to claim 7, Barcwicz/Akamatsu/Nystrom discloses the method of claim 1.
Barcwicz/Akamatsu does not explicitly disclose wherein the at least one positioning post is made of copper.
In an analogous art, Nystrom discloses wherein the at least one positioning post is made of copper (Para 0070 – Fig. 7).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu’s device by having Nystrom’s disclosure in order to improve the alignments of different components of a semiconductor device.
With respect to claim 8, Barcwicz discloses wherein each of the at least one positioning post comprises a top surface and a side surface, the top surface faces away from the substrate, and the side surface connects the top surface and the substrate (Fig. 5A – 106 comprises of a top surface and side surfaces, top surface of 106 faces away from 102).
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Barwicz/Akamatsu/Nystrom in view of McLeod et al. (US 2012/0318855, hereinafter McLeod).
With respect to claim 2, Barwicz/Akamatsu/Nystrom discloses the method of claim 1.
Barwicz/Akamatsu/Nystrom does not explicitly disclose wherein forming the at least one positioning post on the substrate comprises: covering a dry film on the surface of the carrier where the plurality of first pads is disposed, and the dry film further covering the first solder paste; defining at least one blind hole in the dry film to partially expose the surface of the substrate; forming one of the at least one positioning post in a corresponding one of the at least one blind hole, and each of the at least one positioning post connected to the substrate; and removing the dry film.
In an analogous art, McLeod discloses wherein forming the at least one positioning post on the substrate comprises: covering a dry film (110 of Fig. 1A (b)) on the surface of the carrier (102) where the plurality of first pads (104 of Fig. 1A (a)) is disposed, and the dry film further covering the first solder paste (Para 0005-0006 – solder paste); defining at least one blind hole (112 of Fig. 1A (c)) in the dry film to partially expose the surface of the substrate; forming one of the at least one positioning post (116 of Fig. 1A(d)) in a corresponding one of the at least one blind hole (116 of Fig. 1A (e) ), and each of the at least one positioning post connected to the substrate; and removing the dry film (Fig. 1A (e)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu/Nystrom’s device by having McLeod’s disclosure in order to provide multilayer lamination and rapid patterning.
With respect to claim 3, Barwicz discloses that the post is formed by electroplating (Para 0049).
Barwicz/Akamatsu/Nystrom does not explicitly disclose wherein the at least one positioning post is formed in the at least one blind hole.
In an analogous art, McLeod discloses wherein the at least one positioning post is formed in the at least one blind hole (Para 0025 – 116).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu/Nystrom’s device by having McLeod’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 4, Barwicz/Akamatsu/Nystrom does not explicitly disclose wherein one positioning post is formed, one blind hole is formed, the positioning post is non-cylindrical, and the blind hole is non-cylindrical.
In an analogous art, McLeod discloses wherein one positioning post is formed, one blind hole is formed, the positioning post is non-cylindrical, and the blind hole is non-cylindrical (Fig. 1A (e) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu/Nystrom’s device by having McLeod’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 5, Barwicz/Akamatsu/Nystrom does not explicitly disclose
wherein at least two positioning posts are formed, at least two blind holes are formed, each of the at least two positioning posts is cylindrical, and each of the at least two blind holes is cylindrical.
In an analogous art, McLeod discloses wherein at least two positioning posts are formed, at least two blind holes are formed, each of the at least two positioning posts is cylindrical, and each of the at least two blind holes is cylindrical (Fig. 1A (f) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu/Nystrom’s device by having McLeod’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 6, Barwicz/Akamatsu/Nystrom does not explicitly disclose
wherein four positioning posts are formed, four blind holes are formed.
In an analogous art, McLeod discloses wherein four positioning posts are formed, four blind holes are formed (Fig. 1A (e)). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Barcwicz/Akamatsu/Nystrom’s device by having McLeod’s disclosure in order to connect different components of a semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899