DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 10-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. Publication No. 2023/0104966 A1; hereinafter Su) in view of Vasen et al. (U.S. Publication No. 2021/0119131 A1; hereinafter Vasen).
With respect to claim 1, Su discloses a semiconductor device comprising: a channel layer [312] including a two-dimensional (2D) semiconductor material; a gate dielectric layer [3151] on a first area of the channel layer; a gate electrode [315] on the gate dielectric layer; and a source electrode [313] and a drain electrode [314] in a second area of the channel layer (see Figure 10). Su fails to disclose wherein the gate dielectric layer includes a high-k dielectric layer and an intermediate dielectric layer, the intermediate dielectric layer is between the high-k dielectric layer and the channel layer, and a dielectric constant of the intermediate layer is less than a dielectric constant of the high-k dielectric layer.
In the same field of endeavor, Vasen discloses wherein the gate dielectric layer [SP] includes a high-k dielectric layer [160] and an intermediate dielectric layer [150], the intermediate dielectric layer is between the high-k dielectric layer and the channel layer [130] (see Figure 10), and a dielectric constant of the intermediate layer is less than a dielectric constant of the high-k dielectric layer (see ¶[0021]; SiON, Al2O3, SiO2). Implementation of a multilayered gate dielectric layer including a high-k dielectric layer and intermediate layer as taught by Vasen in order to properly provide electrical isolation of the gate structure and allow for isolation of the channel structure to prevent nucleation of dielectric materials (see Vasen ¶[0023]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Su and Vasen discloses wherein the intermediate dielectric layer includes a material having a dielectric constant of 9 or less (see Vasen ¶[0021]; SiO2 has a dielectric constant of 3.9).
With respect to claim 3, the combination of Su and Vasen fails to explicitly disclose wherein a thickness of the intermediate dielectric layer is about 0.5 nm to about 2 nm, however it has been held that [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the proper thickness of the intermediate dielectric layer could be realized based on routine experimentation to properly insulate the gate electrode from the 2D channel.
With respect to claim 4, the combination of Su and Vasen discloses wherein the intermediate dielectric layer includes at least one of C, Si, B, N, O, and Al (see Vasen ¶[0021]).
With respect to claim 5, the combination of Su and Vasen discloses wherein wherein the intermediate dielectric layer includes a crystalline material (see Vasen ¶[0021]).
With respect to claim 6, the combination of Su and Vasen discloses wherein the intermediate dielectric layer includes grains having smaller sizes than grains of the 2D semiconductor material of the channel layer (see Su ¶[0072] and Vasen ¶[0021]).
With respect to claim 7, the combination of Su and Vasen fails to explicitly disclose wherein the intermediate dielectric layer includes a crystalline material having a grain size of 50 nm or less. However, based on the disclosure, it appears that this range is noncritical. It has been held that W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to determine the optimal the crystalline grain size of the intermediate dielectric layer based on routine experimentation to allow for uniform production of the 2D semiconductor material of the channel layer.
With respect to claim 10, the combination of Su and Vasen discloses wherein the 2D semiconductor material of the channel layer includes one to ten layers (See Su ¶[0070]).
With respect to claim 11, the combination of Su and Vasen discloses wherein the 2D semiconductor material of the channel layer includes one to five layers (See Su ¶[0070]).
With respect to claim 12, the combination of Su and Vasen discloses wherein the 2D semiconductor material of the channel layer includes a material having a bandgap of about 0.1 eV to about 3.0 eV (See ¶[0070]; MoS2).
With respect to claim 13, the combination of Su and Vasen discloses wherein the 2D semiconductor material includes transition metal dichalcogenide (TMD), black phosphorous, or graphene (See ¶[0070]; MoS2).
With respect to claim 14, the combination of Su and Vasen discloses wherein the TMD includes a metal element and a chalcogen element, the metal includes one of Mo, W, Nb, Sn, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen element includes one of S, Se, and Te (See ¶[0070]; MoS2).
With respect to claim 15, the combination of Su and Vasen discloses wherein the TMD includes at least one of MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MoSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, and SnTe2 (See ¶[0070]; MoS2).
With respect to claim 18, the combination of Su and Vasen discloses wherein the gate electrode includes metal, conductive nitride, or conductive oxide (see ¶[0076]).
With respect to claim 19, the combination of Su and Vasen discloses wherein the source electrode and the drain electrode include a metal material (see ¶[0072]).
With respect to claim 20, the combination of Su and Vasen discloses an electronic apparatus comprising the semiconductor device according to claim 1 (See ¶[0071]).
Claim(s) 8 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Vasen as applied to claim 1 above, and further in view of Yoo (U.S. Publication No. 2018/0240804 A1).
With respect to claim 8, the combination of Su and Vasen fails to disclose wherein the intermediate dielectric layer includes an amorphous material. In the same field of endeavor, Yoo teaches wherein the intermediate dielectric layer [115] includes an amorphous material (See ¶[0021]). Implementation of an amorphous material as taught by Yoo is a functional equivalent to the materials utilized by the combination of Su and Vasen (see ¶[0021]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 16, the combination of Su and Vasen fails to disclose a ferroelectric layer between the high-k dielectric layer and the intermediate dielectric layer. In the same field of endeavor, Yoo teaches a ferroelectric layer [10] between the high-k dielectric layer [145] and the intermediate dielectric layer [115] (See Figure 1 ¶[0021-0022], ¶[0031]). Implementation of a ferroelectric layer between the high-k dielectric layer and the intermediate dielectric layer as taught by Yoo in order to improve switching characteristics of the transistor structures (see ¶[0031]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 17, the combination of Su, Vasen and Yoo discloses wherein the ferroelectric layer includes at least one of an oxide ferroelectric material, a polymer ferroelectric material, and a fluoride ferroelectric material (see Yoo ¶[0028]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Vasen as applied to claim 1 above, and further in view of Dimitrakopoulos et al. (U.S. Publication No. 2009/0101892 A1; hereinafter Dimitrakopoulos)
With respect to claim 9, the combination of Su and Vasen fails to disclose wherein the intermediate dielectric layer includes a 2D material.
In the same field of endeavor, Dimitrakopoulos teaches a intermediate dielectric layer [18] including a 2D material (see ¶[0040]). Implementation of a 2D material for the intermediate dielectric material of the combination of Su and Vasen, as taught by Dimitrakopoulos, allows for more ordered orientation of channel structures deposited thereon (see ¶[0040]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818