DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 3/8/2026 "Reply" elects with traverse Invention I, Species A and identifies as reading on claims 1-17.
In the restriction requirement Examiner has set forth why the restriction requirement is proper. Applicant contends that FIGs. 5A, 5B, and 5C are intermediate stages, each capable of forming the final device. This argument is not persuasive as the intermediate stages shown in FIGs. 5A, 5B, and 5C are mutually exclusive intermediate stages. Accordingly, the restriction requirement is maintained and Examiner has withdrawn claims 18-20 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Narazaki (US Pub. No. 2014/0299917).
Regarding claim 1, in FIG. 3, Narazaki discloses an electrostatic discharge protection device, comprising: a semiconductor substrate (10A); a first well region (14) having a first conductivity type (P) located in the semiconductor substrate; and a second well region (16) having the first conductivity type located in the semiconductor substrate and adjacent to the first well region, wherein a first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles, and wherein the first well region and the second well region have different doping concentrations (paragraph [0034]).
Regarding claim 2, in FIG. 3, Narazaki discloses that a first doping concentration of the first well region is less than a second doping concentration of the second well region (paragraph [0034]).
Regarding claim 3, in FIG. 3, Narazaki discloses that the first bottom of the first well region has a wave bottom surface and the second bottom of the second well region has an arc bottom surface.
Regarding claim 4, in FIG. 3, Narazaki discloses that the wave bottom surface of the first well region includes a plurality of wave crests and a plurality of wave troughs, wherein the wave crests are closer to a top surface (e.g. surface of 10A closest to 40) of the semiconductor substrate than the wave troughs.
Regarding claim 5, in FIG. 3, Narazaki discloses that the first well region has first sub-regions and second sub-regions alternately arranged with the first sub-regions, wherein the wave troughs are the bottom surface of the first sub-regions, and the wave crests are the bottom surface of the second sub-regions.
Regarding claim 6, in FIG. 3, Narazaki discloses that the first sub-regions have a first depth, and the second sub-regions have a second depth that is different from the first depth (as measured from the 10a/40 interface).
Regarding claim 8, in FIG. 3, Narazaki discloses that the arc bottom surface of the second well region only includes one wave trough that protrudes in a direction away from the top surface of the semiconductor substrate.
Regarding claim 14, in FIG. 3, Narazaki discloses an electrostatic discharge protection device, comprising: a semiconductor substrate (10A); a first well region (14) having a first conductivity type (P) located in the semiconductor substrate; and a second well region (16) having the first conductivity type located in the semiconductor substrate and adjacent to the first well region, wherein a first number (several) of first arc bottoms of the first well region is different from a second number of second arc bottoms (one) of the second well region, and wherein the first well region and the second well region have different doping concentrations (paragraph [0034]).
Regarding claim 15, in FIG. 3, Narazaki discloses that the first number of the first arc bottoms of the first well region is greater than or equal to 2, and the second number of second arc bottoms of the second well region is equal to 1.
Regarding claim 16, in FIG. 3, Narazaki discloses that the first arc bottoms are connected to each other in turn to form a wave bottom surface of the first well region.
Allowable Subject Matter
Claims 7, 9-13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art failed to disclose or reasonably suggest the claimed electrostatic discharge protection device particularly characterized by the first depth is measured from the bottommost point of one of the wave troughs to a top surface of the first well region, and the second depth is measured from the topmost point of one of the wave crests to the top surface of the first well region.
Regarding claim 9, the prior art failed to disclose or reasonably suggest the claimed electrostatic discharge protection device particularly characterized by a third depth measured from the bottommost point of the wave trough of the second well region to a top surface of the second well region is equal to the first depth.
Regarding claims 10-13, the prior art failed to disclose or reasonably suggest the claimed electrostatic discharge protection device particularly characterized by a fourth well region having the second conductivity type located in the semiconductor substrate and separated from the first well region and the second well region, wherein a third bottom of the third well region is connected to a fourth bottom of the fourth well region, and wherein the third bottom of the third well region and the fourth bottom of the fourth well region have different profiles and different doping concentrations.
Regarding claim 17, the prior art failed to disclose or reasonably suggest the claimed electrostatic discharge protection device particularly characterized by a first depth measured from the bottommost point of one of the first arc bottoms of the first well region to a top surface of the first well region is equal to a second depth measured from the bottommost point of the second arc bottom of the second well region to a top surface of the second well region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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