.DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/27/2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11,901,290 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current invention is broader than the issued patent. The features for the current invention have been recited in the issued patent such as one or more bitcells of one or more bitcell arrays, wherein a wordline is at least partially disposed within a backside metal layer. The issued patent did not mention a macro memory unit. However, the issued patent claims memory cell which is well-known in the art for the memory cell to be implanted on a memory device. In addition, the current application recites the wordline or bit lines are “independent of a rail.” However, it is inherent the word lines and bit lines are independent of other rails in the memory devices such as power supply rails, address line, global lines, control signal lines…etc.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 11-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sisodia et al. (US 2022/0223514 A1).
Regarding claim 1, Sisodia teaches an integrated circuit comprising:
a memory macro unit comprising: one or more bitcells of one or more bitcell arrays, wherein a wordline or a bitline is at least partially disposed, independent of a rail, within a backside metal layer of the memory macro unit (Fig. 3, the word line RWL is partially disposed within a backside metal layer of the memory macro unit. metal rail 318 carry only the signal for the RWL, which is part of the word line RWL. In addition, “a rail” is very broad term, which can be any rail in the memory device. RWL is independent of other rails in the memory device, such as VDD rails, VSS rails, WWL rail and bit lines).
Regarding claim 2, Sisodia further teaches the integrated circuit of claim 1, wherein the wordline or the bitlines is coupled to the one or more bitcells of the one or more bitcell arrays and wherein disposed within the backside metal layer comprises the wordline or the bitline being patterned as part of a metallization level of the backside metal layer of the memory macro unit (Fig. 3, the bitline and word line are coupled to one or more bitcells. The wordline RWL is part of the metallization level of the backside layer. RWL is formed in the backside metal layer BM1/BM1).
Regarding claim 3, Sisodia further teaches the integrated circuit of claim 1, wherein the memory macro unit further comprises: control circuitry configured to enable the wordline or the bitline to control the one or more bitcells of the one or more bitcell arrays (¶0014).
Regarding claim 4, Sisodia further teaches the integrated circuit of claim 3, wherein the wordline comprises a first read wordline, and wherein the control circuitry is configured to enable the first read wordline (Fig. 3, RWL is a read word line).
Regarding claim 5, Sisodia further teaches the integrated circuit of claim 4, wherein: a second read wordline is at least partially disposed on a first frontside metal layer (memory array have a plurality of RWL. Fig. 3, shows RWL is partially disposed on a first frontside metal layer M0); and a first write wordline is at least partially disposed on a second frontside metal layer (Fig. 3, WWL is at least partially disposed on a second frontside metal layer M1, M2 or M4).
Regarding claim 6, Sisodia further teaches the integrated circuit of claim 5, wherein the control circuitry is configured to enable the second read wordline and the first write wordline on the respective first and second frontside metal layers (Fig. 3, during access operations for the memory cells, the second read wordline and the first write wordlines will be enabled).
Regarding claim 7, Sisodia further teaches the integrated circuit of claim 3, wherein the bitline comprises a first bitline, and wherein the control circuitry is configured to enable the first bitline (Fig. 3, bitline BL).
Regarding claim 11, the integrated circuit of claim 3, further comprising: one or more word-line decoder blocks; and respective input/output (I/O) circuitry for each of the one or more bitcell arrays, wherein: the one or more bitcell arrays are coupled to the one or more word-line decoder blocks; and the control circuitry is coupled to the one or more word-line decoder blocks, the respective input/output (I/O) circuitry, and the one or more bitcell arrays, wherein the wordline extends between a wordline decoder block of the one or more word-line decoder blocks and at least one of the one or more bitcell arrays (decoders and input/output circuitry are inherent for an SRAM memory device. The wordline decoder will be coupled to the wordlines WWL and RWL. RWL and WWL will be extended and coupled to the wordline decoder).
Regarding claim 12, Sisodia further teaches the integrated circuit of claim 1, wherein the backside metal layer is coupled to the one or more bitcell arrays, a first wordline is disposed at least partially within the backside metal layer, and a second wordline is disposed at least partially within a front-side metal layer. (Fig. 3, RWL is disposed partially within the backside metal layer BM0/BM1 and second wordline WWL is disposed partially within the frontside metal layers M2 or M4).
Regarding claims 13-17 and 20, the claims have similar limitation as claims 1-7 and 11-12. Therefore, the claims are rejected under the same grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-10 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia as applied to claim 1 above, and further in view of Chen et al. (US 2022/0077857 A1).
Regarding claim 8, Sisodia further teaches the integrated circuit of claim 7, wherein:
A first portion of the bitlines to be disposed on the backside metal layer and a second portion of the bitlines to be disposed on a frontside metal layer (Fig. 3). The claims did not recites the first bitline for the first tray and the first bitlines for the second tray to be different. In order to expedite the prosecution for the case, Chen is used.
Chen teaches the first bitline is disposed on the back-side metal layer for a first range of bitcells of a first bitcell array of the one or more bitcell arrays; and the first bitline is disposed on a frontside metal layer for a second range of bitcells of second bitcell array of the one or more bitcell arrays or the first bitcell array (Fig. 4, the first bit lines for the first tray 408A are routed on the back-side metal layer BM0. The first bitlines for the second tray 408B are disposed on a frontside metal layer M2).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use Chen teaching by disposing bitlines on the back-side metal layer in order improve area efficiency of the memory and increase density, see¶0002.
Regarding claim 9, Chen further teaches the integrated circuit of claim 8, wherein: a second bitline is disposed on the frontside metal layer for the first range of the one or more bitcells of the first bitcell array; and the control circuitry is configured to enable the second bitline (Fig. 4, second bitline bl_top(M2)).
Regarding claim 10, Sisodia further teaches the integrated circuit of claim 8, further comprising: a through silicon via (TSV) configured to route the first bitline from the backside metal layer to the frontside metal layer (buried transition vias (BTV) see ¶0034 to ¶0036).
Regarding claims 18-19, the claims have similar limitations as claims 8-10 except the claims were written in a method format. Therefore, the claims are rejected under the same grounds of rejection for the same reason.
Response to Arguments
Applicant's arguments filed 11/06/2025 have been fully considered but they are not persuasive.
Applicant’s arguments regarding the double patenting rejection “It is respectfully submitted that Sisodia-Chen's claims, which are directed to a device that adapts a backside power/ground rail to carry a WL signal, is patentably distinct from claims 1-20 pertaining to devices with a WL or BL disposed within the backside metal layer, independent of a rail.” However, there is no evidence that power/ground rail carry the WL as alleged by applicant’s representative. In addition, the current application recites the wordline or bit lines are “independent of a rail.” However, it is inherent the word lines and bit lines are independent of other rails in the memory devices such as power supply rails, address line, global lines, control signal lines…etc.
Applicant’s representative argues on page 8 and 9 “Sisodia-Chen, ,-I,J 0021, 0024. Sisodia-Chen describes a bitcell layout architecture in which the read wordline (RWL) is coupled to a buried backside metal rail 318 (BMO/BM1 ). Further, Sisodia-Chen describes RWL as being "formed with and/or coupled to" the buried backside metal rail 318 (BMO/BM1 ). Sisodia-Chen's adaptation of the backside metal rail 318 (BM0/BM1) in the backside PON from power/ground to carry the RWL signal by coupling to frontside RWL does not contemplate that the RWL itself is disposed, independent of a rail, within a backside metal layer. Claim 1 pertains to disposing within a backside metal layer all or part of a WL or BL during metallization and patterning of the backside metal layer, which, as expressly set forth in amended claim 1, does not involve adapting/repurposing a rail by coupling it to a frontside WL or BL.”
Applicant’s representative alleges that Sisodia-Chen discloses that the RWL uses the power/ground rails to carry the RWL signal. If this is the case, then RWL will always be coupled to ground level or power level (VDD). If RWL is always coupled to ground, then all the access transistor will be off and memory device can’t access any memory cell. And if RWL is always coupled to power rail, then the access transistors for all the memory cells will be open and the memory can’t select any memory cell because all the memory cells are selected as a result of power level is applied to all the access transistors. Therefore, there are no evidence that the power/ground rails carry the RWL signal. Most bit cells have the word lines and bit lines are routed through the front side mentalization layer, but Sisodia-Chen utilizes the backside metal layer to route the read word line (RWL), which metal rail 318 is used for RWL only. There are no evidence that 318 is used for anything beside carrying signal for RWL. Therefore, Sisodia still teaches all the claimed features and rejection is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
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