DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7, 8, 10, 12, 14, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7, 8, 10, and 12 recites the limitation “when an electrostatic discharge event occurs…” This limitation renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claims 14 and 15 recites the limitation "the same structure" in line 7. There is insufficient antecedent basis for this limitation in the claims and therefore this limitation renders the claims indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, and 5-15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Peng (US 2021/0082906).
Regarding claim 1, Peng discloses an electrostatic discharge protection device, comprising (Fig.11C): a P-type semiconductor substrate (PS); and a first electrostatic discharge protection unit located in the P-type semiconductor substrate (PS) and used to protect a first circuit, wherein the first electrostatic discharge protection unit comprises: a first N-type well region (NW1) ; a first N-type doped region (DpN+) located in the first N-type well region (NW1); a first P-type doped region (DpP+) located in the first N-type well region (NW1), wherein the first P-type doped region (DpP+) and the first N-type doped region (DpN+) are arranged side-by-side and spaced apart from each other; a first P-type well region (PW2) adjacent to the first N-type well region (NW1); a second N-type doped region (Dn’N+) located in the first P-type well region (PW2); a second N-type well region (NW3) arranged side-by-side with the first N-type well region (NW1); a second P-type doped region (Dp’P+) located in the second N-type well region (NW3); a second P-type well region (PW3) adjacent to the second N-type well region (NW3); a third N-type doped region (DnN+) located in the second P-type well region (PW3); and a third P-type doped region (DnP+) located in the second P-type well region (PW3), wherein the third P-type doped region (DnP+) and the third N-type doped region (DnN+) are arranged side-by-side and spaced apart from each other, wherein the first P-type doped region (DnP+) and the third N-type doped region (DnN+) of the first electrostatic discharge protection unit are electrically connected to a common bus (I/O), wherein the first N-type doped region (DpN+) and the second P-type doped region (Dp’P+) of the first electrostatic discharge protection unit are electrically connected to a power supply terminal of the first circuit (VDD), and wherein the second N-type doped region (Dn’N+) and the third P-type doped region (Dn’P+) of the first electrostatic discharge protection unit are electrically connected to a ground terminal of the first circuit (VSS).
Regarding claim 2, Peng discloses wherein the first P-type doped region (DnP+) is laterally located between the first N-type doped region (DpN+) and the second N-type doped region (Dn’N+).
Regarding claim 3, Peng discloses wherein the third N-type doped region (DnN+) is laterally located between the second P-type doped region (DpP+) and the third P-type doped region (Dn’P+).
Regarding claim 5, Peng discloses wherein the second P-type well region (Fig.7B, PW2) of the first electrostatic discharge protection unit is a portion of the first P-type well region (PW1), so that the third P-type doped region (Dp’P+) is laterally located between the second N-type doped region (DnN+) and the third N-type doped region (DpP+).
Regarding claim 6, Peng discloses wherein the first P-type doped region, the first N-type well region and the first N-type doped region form a first parasitic diode, and wherein the third P-type doped region, the second P-type well region and the third N-type doped region form a second parasitic diode ([0095]).
Regarding claim 7, Peng discloses wherein when an electrostatic discharge event occurs between the common bus and the power supply terminal of the first circuit, the first parasitic diode is triggered to ON ([0095]).
Regarding claim 8, Peng discloses wherein when an electrostatic discharge event occurs between the ground terminal of the first circuit and the common bus, the second parasitic diode is triggered to ON ([0095]).
Regarding claim 9, Peng discloses wherein: the first P-type doped region (DpP+), the first N-type well region (DpN+) and the first P-type well region (PW2) form a first parasitic bipolar junction transistor, the second N-type doped region (Dn’N+), the first P-type well region (PW2) and the first N-type well region (NW1) form a second parasitic bipolar junction transistor ([0092]), a base (PW2) of the first parasitic bipolar junction transistor is electrically connected to a collector of the second parasitic bipolar junction transistor ([0094]), and a base of the second parasitic bipolar junction transistor is electrically connected to the collector of the first parasitic bipolar junction transistor to form a first parasitic semiconductor-controlled rectifier, an emitter of the first parasitic bipolar junction transistor is electrically connected to the common bus (I/O) and an anode of the first parasitic diode, the base of the first parasitic bipolar junction transistor is electrically connected to the power supply terminal (VDD) of the first circuit and a cathode of the first parasitic diode ([0092]), and an emitter of the second parasitic bipolar junction transistor is electrically connected to the ground terminal of the first circuit (Fig.11C; [0095])).
Regarding claim 10, Peng discloses wherein when an electrostatic discharge event occurs between the common bus and the ground terminal of the first circuit, the first parasitic diode is triggered to ON, and the first parasitic bipolar junction transistor and the second parasitic bipolar junction transistor are triggered to ON, so that the first parasitic semiconductor-controlled rectifier is accordingly triggered to ON ([0095]).
Regarding claim 11, Peng discloses wherein: the third N-type doped region (DnN+), the second P-type well region (Dn’P+) and the second N-type well region (NW3) form a third parasitic bipolar junction transistor (Fig.11C), the second P-type doped region (Dn’P+), the second N-type well region (Dp’N+) and the third P-type doped region (DnP+) form a fourth parasitic bipolar junction transistor, a base of the third parasitic bipolar junction transistor is electrically connected to a collector (NW3) of the fourth parasitic bipolar junction transistor ([0094]), a base of the fourth parasitic bipolar junction transistor is electrically connected to a collector of the third parasitic bipolar junction transistor to form a second parasitic semiconductor-controlled rectifier, an emitter of the third parasitic bipolar junction transistor is electrically connected to the common bus (I/0) and a cathode of the second parasitic diode, the base of the third parasitic bipolar junction transistor (PW2) is electrically connected to the ground terminal of the first circuit and an anode of the second parasitic diode, and an emitter of the fourth parasitic bipolar junction transistor is electrically connected to the power supply terminal of the first circuit (Fig.11C; [0092]-[0094]).
Regarding claim 12, Peng discloses wherein when an electrostatic discharge event occurs between the power supply terminal of the first circuit and the common bus, the second parasitic diode is triggered to ON, and the third parasitic bipolar junction transistor and the fourth parasitic bipolar junction transistor are triggered to ON, so that the second parasitic semiconductor-controlled rectifier is accordingly triggered to ON ([0095]).
Regarding claim 13, Peng discloses a second electrostatic discharge protection unit (ESP2) located in the P-type semiconductor substrate and used to protect the first circuit, wherein the first electrostatic discharge protection unit and the second electrostatic discharge protection unit are spaced apart from each other and have the same structure, wherein a first P-type doped region (DpP+) and a third N-type doped region (DnN+) of the second electrostatic discharge protection unit are electrically connected to an input/output terminal (I/O) of the first circuit, a first N-type doped region and a second P-type doped region of the second electrostatic discharge protection unit are electrically connected to the power supply terminal of the first circuit, and wherein a second N-type doped region and a third P-type doped region of the second electrostatic discharge protection unit are electrically connected to the ground terminal of the first circuit (Fig.2B).
Regarding claim 14, Peng discloses a third electrostatic discharge protection unit (ESDP3) located in the P-type semiconductor substrate and used to protect a second circuit, wherein the first electrostatic discharge protection unit (ESPD1)and the third electrostatic discharge protection unit (ESPD3) are spaced apart from each other and have the same structure ([0040]), wherein a first P-type doped region and a third N-type doped region of the third electrostatic discharge protection unit are electrically connected to the common bus (I/O), a first N-type doped region and a second P-type doped region of the third electrostatic discharge protection unit are electrically connected to a power supply terminal (VDD) of the second circuit, and wherein a second N-type doped region and a third P-type doped region of the third electrostatic discharge protection unit are electrically connected to a ground terminal (VSS) of the second circuit ([0035]).
Regarding claim 15, Peng discloses a fourth electrostatic discharge protection unit (ESDP4) located in the P-type semiconductor substrate and used to protect the second circuit, wherein the third electrostatic discharge protection unit (EPD3) and the fourth electrostatic discharge protection unit are spaced apart from each other and have the same structure ([0035]), wherein a first P-type doped region (DpP+)and a third N-type doped region (DnP+) of the fourth electrostatic discharge protection unit are electrically connected to an input/output terminal (I/0) of the second circuit, a first N-type doped region (DpN+) and a second P-type doped region (DpP+) of the fourth electrostatic discharge protection unit are electrically connected to the power supply terminal (VDD) of the second circuit, and wherein a second N-type doped region (Dm’N+) and a third P-type doped region (DnP+) the fourth electrostatic discharge protection unit are electrically connected to the ground terminal (VSS) of the second circuit ([0089]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claim 1 above, and further in view of Xu (US 2003/0040542).
Regarding claim 4, Peng does not disclose wherein the second N-type well region of the first electrostatic discharge protection unit is a portion of the first N-type well region, so that the first N-type doped region is laterally located between the first P-type doped region and the second P-type doped region.
Xu however discloses wherein the second N-type well region of the first electrostatic discharge protection unit is a portion of the first N-type well region (Fig.8, numeral NW4), so that the first N-type doped region (6) is laterally located between the first P-type doped region (7) and the second P-type doped region (17).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Peng with Xu to have the second N-type well region of the first electrostatic discharge protection unit is a portion of the first N-type well region, so that the first N-type doped region is laterally located between the first P-type doped region and the second P-type doped region for the purpose of reducing leakage current during normal operation of the chip (Xu, [0041]).
Conclusion
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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