DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 11/24/2023 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 03/11/2025, 04/01/2025 & 05/28/2025. The information disclosed therein was considered.
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-12 & 19-20) in the reply filed on 11/10/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 9, 12 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Chang et al (US20220367489).
Regarding claim 1, Chang discloses a memory device(FIG 1; 100), comprising: a memory array comprising a plurality of memory cells(104); wherein at least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit(FIG 2B; [0033] discloses a short circuit occurring in an insulating material of C when applied a break down voltage or higher, wherein broken-down insulating material corresponding to a first logic value e.g., logic 0); and wherein at least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit(FIG 2C; [0034] material not yet broken down represented by logic 1 in open circuit, e.g., opposite of short circuit and logic value e.g., the next memory cell on the same memory array).
Regarding claim 2, Chang discloses wherein the memory cells each include an efuse memory cell (FIG 1; [0027] discloses 200 being e-fuse memory cell).
Regarding claim 3, Chang discloses wherein the first memory cell includes a transistor formed along a major surface of a substrate (FIG 1, 2B & 4A; [0042] discloses 400 e.g., cell 200 having transistor 410 (222) formed on a first side of substate 408).
Regarding claim 6, Chang discloses wherein the second memory cell includes a transistor formed along a major surface of a substrate (FIG 1, 2C & 4A; [0042] discloses 400 e.g., cell 200 having transistor 410 (222) formed on a first side of substate 408. Note the next memory cell on the array).
Regarding claim 9, Chang discloses wherein the memory cells each include an anti-fuse memory cell (FIG 1; [0027] discloses 200 being anti-fuse memory cell).
Regarding claim 12, Chang discloses wherein respective positions of the first memory cell and second memory cell in the memory array are preconfigured (FIG 1 & 3; [0040] discloses 200A and 200B and so on are preconfigured e.g., stored values).
Claim(s) 19 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Park et al (US20160078962).
Regarding claim 19, Park discloses a method(FIG 1,3 & 7; [0038-0043 & 0053]), comprising: forming a plurality of transistors along a major surface of a substrate(FIG 1 & 7; plurality transistors e.g. 411 421 412 422 on substrate 102); and forming a plurality of metal tracks over the plurality of transistors(stack up metals e.g., 120, 320, 220 with 122, 132 222 232; note WLs and BLs and PL are considered metal tracks), wherein a first one of the transistors, together with at least a first one of the plurality of metal tracks, collectively form a first memory cell(WL1 with transistor 421), in which the first metal track forms a short circuit coupled to the first transistor(FIG 1, 3 & 7; [0034] when memory cell is in conductive state e.g., short state) ; and wherein a second one of the transistors, together with at least a third one and a fourth one of the plurality of metal tracks collectively form a second memory cell(422 with WL2 and BL2), in which the third and fourth metal tracks form an open circuit coupled to the second transistor([0034] when memory cell is formed to initially have an insulated stated e.g., open state).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al in view of Chang et al.
Regarding claim 20, Park discloses short circuit and open circuit (FIG 1, 3 & 7; [0034] when memory cell is in conductive state e.g., short state and insulated stated e.g., open).
However, Park does not disclose wherein the first memory cell, by default, permanently presents a first logic state based on the short circuit, and the second memory cell (FIG 2B; [0033] discloses a short circuit occurring in an insulating material of C when applied a break down voltage or higher, wherein broken-down insulating material corresponding to a first logic value e.g., logic 0), by default, permanently presents a second logic state based on the open circuit.
In the same field of endeavor, Chang discloses wherein the first memory cell, by default, permanently presents a first logic state based on the short circuit, and the second memory cell, by default, permanently presents a second logic state based on the open circuit (FIG 2C; [0034] material not yet broken down represented by logic 1 in open circuit, e.g., opposite of short circuit and logic value e.g., the next memory cell on the same memory array).
Park and Chang are analogous art because they are all directed to a memory device comprising a functionality that operates in an open and close circuitry, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Park to include Chang because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Chang in the teachings of Park for the benefits avoiding a degradation in the memory device over time that is caused by high voltage endurance. [0002 Chang].
Allowable Subject Matter
Claims 21-26 are allowed.
Claims 4-5, 7-8 & 10-11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tsuda et al (US20130098424 FIG 4-2 & 7; claim 1 and [0059] discloses metal stacked and short and open circuits).
Srivastava et al (US20220129166 FIG 1; discloses memory 100 comprising NVM memory 160, comprising e-fuses cell 162A & 162B having a default values).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827