DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/31/2026 has been entered.
Election/Restrictions
Claim 8 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/02/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-7, 9-10, 12-15 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen (US 2023/0343556) in view of Luu et al (US 2024/0404788) and Radomski et al. (US 2025/0174436).
Regarding claim 1, Nguyen discloses a bias supply [e.g. fig. 2/6/11/16] comprising: an output node [e.g. Vout/310/210]; power circuitry [e.g. bias supply] configured to apply an asymmetric periodic voltage waveform at the output node wherein the asymmetric periodic voltage waveform comprises: a first section that begins with a first negative voltage [see Vout at t0 fig. 4/5/19] and changes during a first transition to a peak voltage [see Vout at t1] before changing during a second transition to a second negative voltage [see Vout at t3]; and a second section that begins with the second negative voltage and comprises a voltage ramp between the second negative voltage and a third negative voltage [see Vout at t4]; and transition circuitry [see at least 620/622, paras. 0044-0049, 0052-0057] configured to adjust a slope of one, or both, of the first and second transitions of the first section. Nguyen does not explicitly disclose to adjust a slope of one, or both, of the first and second transitions of the first section. However, to adjust a slope of a pulse/waveform is well-known. For example, Luu discloses to adjust a slope of one, or both, of the first and second transitions of the first section [see paras. 0122-0123, fig. 23, para. 0112, fig. 16].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nguyen in accordance with the teaching of Luu regarding slope in order to provide various needs [see paras. 0122-0123, 0112].
The combination does not disclose transition circuitry comprising a variable reactance coupled between the power circuitry and the output node. However, Radomski discloses transition circuitry comprising a variable reactance [e.g. 718/712 fig. 7; 518b fig. 5] coupled between power circuitry [e.g. 712b fig. 7; 512b fig. 5] and an output node configured to adjust a slope by adjusting the variable reactance [see at least paras. 0074, 0079]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nguyen and Luu in accordance with the teaching of Radomski regarding impedance in order to provide improved impedance tuning [see para. 0079].
Regarding claim 3, the combination discussed above discloses the bias supply of claim 1, wherein the transition circuitry comprises a variable inductance [see at least para. 0074 Radomski].
Regarding claim 4, the combination discussed above discloses the bias supply of claim 1, wherein the transition circuitry comprises a variable capacitance [see at least para. 0074 Radomski].
Regarding claim 6, the combination discussed above discloses the bias supply of claim 1, wherein the power circuitry comprises a switch network [see at least switch network fig. 7/10/15 Nguyen] and at least one power supply [e.g. 216/218 fig. 7/10/15].
Regarding claim 7, the combination discussed above discloses the bias supply of claim 6, wherein the switch network comprises: at least two switches [e.g. S1, S2 fig. 14A/18A Nguyen] wherein, when closed, a first of the at least two switches causes the bias supply to apply the peak voltage, and when closed, another of the at least two switches causes the bias supply to apply the second negative voltage.
Regarding claim 9, the combination discussed above discloses the bias supply of claim 6, wherein the bias supply comprises at least two switches and at least two power supplies.
Regarding claim 10, the combination discussed in claim 1 discloses a method comprising: applying a first section of an asymmetric periodic voltage waveform to a plasma processing chamber [e.g. 101 fig. 1 Nguyen], the first section begins with a first negative voltage and changes during a first transition to a second, peak voltage before changing during a second transition to a second negative voltage; applying a second section of the asymmetric periodic voltage waveform that begins with the second negative voltage and comprises a voltage ramp between the second negative voltage and a third negative voltage; and adjusting a slope of one, or both, of the first and second transitions of the first section by adjusting a variable reactance. Please see rejection of claim 1
Regarding claim 12, the combination discussed above discloses the method of claim 10, wherein adjusting the variable reactance comprises adjusting a variable inductance [see at least para. 0074 Radomski].
Regarding claim 13, the combination discussed above discloses the method of claim 10, wherein adjusting the variable reactance comprises adjusting a variable capacitance [see at least para. 0074 Radomski].
Regarding claim 14, the combination discussed above discloses the method of claim 10, wherein adjusting the variable reactance comprises adjusting a combination of a variable capacitance and variable inductance [see at least para. 0074 Radomski].
Regarding claim 15, the combination discussed in claim 1 discloses a non-transitory processor-readable storage medium [see at least paras. 0103, 0104, 0107 Nguyen] having instructions [see at least paras. 0103-0108] embodied thereon, the instructions are executable by a processor and/or for programming a field programmable gate array [see at least paras. 0103-0108 Nguyen], the instructions comprising instructions for: applying a first section of an asymmetric periodic voltage waveform to a plasma processing chamber, the first section begins with a first negative voltage and changes during a first transition to a second, peak voltage before changing during a second transition to a second negative voltage; applying a second section of the asymmetric periodic voltage waveform that begins with the second negative voltage and comprises a voltage ramp between the second negative voltage and a third negative voltage; and adjusting a slope of one, or both, of the first and second transitions of the first section by adjusting a variable reactance. Please see rejection of claim 1
Regarding claim 17, the combination discussed above discloses the non-transitory processor-readable storage medium of claim 15, wherein the instructions comprise instructions for adjusting a variable inductance [see at least para. 0074 Radomski].
Regarding claim 18, the combination discussed above discloses the non-transitory processor-readable storage medium of claim 15, wherein the instructions comprise instructions for adjusting a variable capacitance [see at least para. 0074 Radomski].
Regarding claim 19, the combination discussed above discloses the non-transitory processor-readable storage medium of claim 15, wherein the instructions comprise instructions for adjusting a combination of a variable capacitance and variable inductance [see at least para. 0074 Radomski].
Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen (US 2023/0343556) in view of Luu et al (US 2024/0404788), Radomski et al. (US 2025/0174436) and Wyse et al (US 9,667,211).
Regarding claim 5, the combination discussed above discloses the bias supply of claim 1, except wherein the transition circuitry comprises a combination of fixed and variable reactive elements. However, it’s well-known to utilize a combination of fixed and variable reactive elements to vary the value of a capacitance/inductance. For example, Wyse discloses utilize a combination of fixed and variable reactive elements to vary the value of a capacitance/inductance [fig. 3 Wyse]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nguyen, Luu and in accordance with the teaching of Wyse regarding reactance in order to utilize well-known fixed and variable reactive elements to vary the value of a capacitance/inductance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 05/31/2026 have been considered but are moot because the new ground of rejection does not rely on a new reference, Radomski et al. (US 2025/0174436), which was not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:00.
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/PATRICK C CHEN/Primary Examiner, Art Unit 2836
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