DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,5-7,9-17,19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication Number 2023/0317546 A1 to Brun et al., “Brun”.
Regarding claim 1, Brun discloses an electronic component (FIG. 1A), comprising:
a semiconductor body (104, ¶ [0047],[0048]);
an active region (front side 106, ¶ [0047]) in a central portion of the semiconductor body; and
a stress release structure (overhang 116, ¶ [0050]-[0053]) for releasing stress (¶ [0019],[0025]) and being formed as a lateral edge portion (112) of the semiconductor body, said lateral edge portion having (e.g. FIG. 1B) a minimum thickness (D1) of not more than 40% of a maximum thickness of the semiconductor body (as pictured and since D1 = 1-3 μm which is less than 40% of the maximum thickness of portion Z1 = 5-12 μm, ¶ [0050] and therefore less than 40% of maximum thickness).
Regarding claim 5, Brun discloses the electronic component according to claim 1, and Brun further discloses wherein said lateral edge portion has a minimum thickness of not more than 20% of the maximum thickness of the semiconductor body.
Regarding claim 6, Brun discloses the electronic component according to claim 1, and Brun further discloses (FIG. 1C) wherein said lateral edge portion has a minimum thickness of zero (point P4, ¶ [0051]) at an exterior edge (112) of the semiconductor body.
Regarding claim 7, Brun discloses the electronic component according to claim 1, and Brun further discloses wherein at least part (surface 1220 of the lateral edge portion has a concave shape (¶ [0127]).
Regarding claim 9, Brun discloses the electronic component according to claim 1, and Brun further discloses wherein the minimum thickness (D1) at the lateral edge portion is not more than 50 µm (D1 = 1-3 μm ¶ [0050]).
Regarding claim 10, Brun discloses the electronic component according to claim 1, and Brun further discloses (FIG. 1E) wherein the stress release structure (116) is delimited by a vertical section (sidewall 120) at an exterior edge (112) of the semiconductor body (104) and by a slanted section connected between said vertical section and a horizontal surface of the semiconductor body, wherein in particular the slanted section is concave (122, ¶ [0050]).
Regarding claim 11, Brun discloses a package (FIG. 1A), comprising: a carrier (136, ¶ [0053]); and an electronic component (within body 104) according to claim 1 and being mounted on the carrier (136); wherein the stress release structure (116) of the electronic component releases stress at an interface between the lateral edge portion and the carrier (¶ [0019],[0025]).
Regarding claim 12, Brun discloses the package according to claim 11, and Brun further discloses wherein the carrier (136) comprises a metallic material (e.g. 134, ¶ [0054]) at the interface with the electronic component (in 104).
Regarding claim 13, Brun discloses a method of manufacturing an electronic component, wherein the method comprises:
forming (e.g. FIG. 6B) an active region (608a, 608b, ¶ [0090]) in a central portion (of each 602) of a semiconductor body; and
forming (e.g. FIG. 8A, 8B) a stress release structure (FIG. 1A overhang 116, ¶ [0050]-[0053]) for releasing stress (¶ [0019],[0025]) as a lateral edge portion of the semiconductor body, said lateral edge portion being formed with a minimum thickness (D1) of not more than 40% of a maximum thickness of the semiconductor body (as pictured and since D1 = 1-3 μm which is less than 40% of the maximum thickness of portion Z1 = 5-12 μm, ¶ [0050] and therefore less than 40% of maximum thickness).
Regarding claim 14, Brun discloses the method according to claim 13, and Brun further discloses wherein the method comprises separating (FIG. 8A,8B) the semiconductor body from a wafer along separation lines so that the stress release structure is formed by said separating (¶ [0098]-[0101]).
Regarding claim 15, Brun discloses the method according to claim 14, and Brun further discloses wherein said separating comprises carrying out a first separation process (e.g. FIG. 8A) penetrating (819) into the wafer, and carrying out a subsequent second separation process (e.g. FIG. 8B) penetrating through (826) the wafer.
Regarding claim 16, Brun discloses the method according to claim 15, and Brun further discloses wherein one or both of the first separation process (FIG. 8A) and the second separation process (FIG. 8B) comprises a mechanical dicing process (cutting tool 814 and 820, ¶ [0099],[0101]).
Regarding claim 17, Brun discloses the method according to claim 15, and Brun further discloses wherein the second separation process comprises a laser dicing process (laser ablation or laser milling or laser chemical etching ¶ [0058],[0059]).
Regarding claim 19, Brun discloses the method according to claim 13, and Brun further discloses wherein the method comprises forming the stress release structure by etching (laser chemical etching, wet and dry etching, reactive ion etching ¶ [0058],[0059]).
Regarding claim 20, Brun discloses the method according to claim 13, and Brun further discloses wherein the method comprises mounting the electronic component on a carrier by soldering (¶ [0060],[0037]-[0038],[0040], conductive contacts 134, ¶ [0054]).
Claims 1-4,8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Number 9,892,989 B1 to Ho et al., “Ho”.
Regarding claim 1, Ho discloses an electronic component (e.g. FIG. 1), comprising:
a semiconductor body (102, column 2 lines 39-48);
an active region (side with bonding pads 118, column 3 lines 8-9) in a central portion of the semiconductor body; and
a stress release structure (overhang having width w1, column 2 lines 44-61) for releasing stress and being formed as a lateral edge portion of the semiconductor body, said lateral edge portion having a minimum thickness of not more than 40% of a maximum thickness of the semiconductor body (since in FIG. 3E first cut has a depth between 70-80% of the thickness of the wafer 300, column 4 lines 41-42, and the thickness of the overhang having width W1 is equal to the thickness of the wafer not cut during the first cut, i.e. (100%) - (70-80%) = 20-30%).
Examiner’s Note: the language of releases stresses is a functional limitation since it has been held that a claim term is functional when it recites a feature "by what it does rather than by what it is" (e.g., as evidenced by its specific structure or specific ingredients). In re Swinehart, 439 F.2d 210, 212, 169 USPQ 226, 229 (CCPA 1971), MPEP 2173.05(g). In the present case, the functional language is deemed satisfied insofar as the structure of the prior art anticipates the claimed limitations and appears structurally similar to Applicant’s disclosed structure, see e.g. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432. See also Bettcher Industries, Inc. v. Bunzl USA, Inc., 661 F.3d 629, 639-40, 100 USPQ2d 1433, 1440 (Fed. Cir. 2011), MPEP 2114 I. INHERENCY AND FUNCTIONAL LIMITATIONS IN APPARATUS CLAIMS.
Regarding claim 2, Ho discloses the electronic component according to claim 1, and Ho further discloses (e.g. FIG. 1) wherein a lateral extension (W1) of the stress release structure between an exterior edge of the semiconductor body (102) and a position at which the semiconductor body reaches its maximum thickness is at least 10% of the maximum thickness of the semiconductor body (W1 = 20 μm column 2 line 56, wafer thickness is 50 μm to 100 μm column 4 line 33).
Regarding claim 3, Ho discloses the electronic component according to claim 2, and Ho further discloses wherein said lateral extension of the stress release structure is at least 20% of the maximum thickness of the semiconductor body (W1 = 20 μm column 2 line 56, wafer thickness is 50 μm to 100 μm column 4 line 33).
Regarding claim 4, Ho discloses the electronic component according to claim 2, and Ho further discloses wherein said lateral extension of the stress release structure is not more than 150 µm (W1 = 20 μm column 2 line 56).
Regarding claim 8, Ho discloses the electronic component according to claim 1, and Ho further discloses wherein the maximum thickness [of the semiconductor body] is in a range from 20 µm to 220 µm (50 μm to 100 μm column 4 line 33).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2023/0317546 A1 to Brun et al., “Brun”, in view of U.S. Patent Application Publication Number 2003/0047543 A1 to Peng et al., “Peng”.
Regarding claim 18, although Brun discloses the method according to claim 14, Brun fails to clearly teach in sufficient detail for anticipation wherein said separating comprises carrying out a single separation process penetrating through the wafer by a laser, in particular by a multi-beam laser or by a liquid-guided laser.
Peng teaches a laser cutter for improved integrated circuit manufacturing equipment (¶ [0009]) which includes a liquid guided laser beam (FIG. 7 ¶ [0010],[0035], liquid source 716, ¶ [0035],[0036]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Brun using a liquid guided laser beam as taught by Peng in order to benefit from relatively stress-free cutting with adequate throughout and without diminished productivity and with fewer damaged wafers (Peng ¶ [0045]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Number 9,343,367 B2 to Goida et al. teaches stress reduction (Title, Abstract) with regions of reduced thickness (9c and 9d dimensions “D” and “l”);
U.S. Patent Application Publication Number 2015/0364376 A1 to Yu et al. teaches (e.g. FIG. 7) a slanted notch (134c, ¶ [0041]) and (e.g. FIG. 8) a concave notch (134d, ¶ [0042]);
U.S. Patent Number 12,062,596 B2 to Zhang et al. teaches (e.g. FIG. 1) a package having recessed regions (width 164) for improving the attaching with an adhesive layer (132, Abstract);
U.S. Patent Number 10,763,223 B2 to Wang et al. teaches a chamfer to reduce packaging stress (Abstract);
U.S. Patent Number 7,456,108 B2 to Fukazawa teaches (e.g. FIG. 4A,4B) a rounded corner region (10c) which can mitigate stress concentration (column 3 lines 11-18).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891