DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/24/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 4-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamaguchi et al. (US Patent Application Publication No. 2012/0106220) (“Yamaguchi”).
Regarding Claim 1, Yamaguchi teaches a capacitor device connected to a semiconductor device (Figure 10 – see connection of C (16s) and Swn/FDn (22n)), the capacitor device comprising : a capacitor element (Figure 10, item 16s) including a first electrode and a second electrode (see Figure 10, electrodes depicted on left and right side of C); a first wiring (Figure 10, item 36s) having a first one end portion connected to the first electrode and a first other end portion connected to a first electrode terminal of the semiconductor device (see electrical connection through devices and terminating at 22n); and a second wiring (Figure 10, item 36) having a second one end portion connected to the second electrode and a second other end portion connected to a second electrode terminal of the semiconductor device (see Figure 10, note connection of 22n and 36 through 34n), wherein a resistor (Figure 10, item R) is provided between the first one end portion and the first other end portion of the first wiring and is electrically connected directly to the first wiring (see Figure 10).
Regarding Claim 2, Yamaguchi further teaches the resistor is a shunt resistor (see Figure 10 and also Figure 20B and ¶0132).
Regarding Claim 4, Yamaguchi further teaches the resistor is sandwiched by the first one end portion and the first other end portion of the first wiring and is included in the first wiring (see Figure 10, note location of R between sections of the first wiring).
Regarding Claim 5, Yamaguchi further teaches the first wiring further includes a first detection terminal (Figure 10, item 36s) provided adjacent to the resistor on the first one end portion, and a second detection terminal (Figure 10, item 26s) provided adjacent to the resistor on the first other end portion.
Regarding Claim 6, Yamaguchi further teaches a sealing member (Figure 10, item 20) sealing the capacitor element, the first wiring including the resistor and the second wiring, with the first other end portion of the first wiring and the second other end portion of the second wiring being exposed (see Figure 10, note item 20 sealing various portion of the claimed elements while leaving other portions exposed).
Regarding Claim 7, Yamaguchi further teaches the first wiring includes a first detection terminal (Figure 10, item 36s) provided adjacent to the resistor on the first one end portion, and a second detection terminal (Figure 10, item 26s) provided adjacent to the resistor on the first other end portion; and one end of the first detection terminal opposite to an other end of the first detection terminal that is connected to the first one end portion and one end of the second detection terminal opposite to an other end of the second detection terminal that is connected to the first other end portion are each exposed from the sealing member (see Figure 10).
Regarding Claim 8, Yamaguchi further teaches a first power supply terminal connected to the first one end portion of the first wiring; and a second power supply terminal connected to the second one end portion of the second wiring, the first and second power supply terminals being connected to a power supply of the capacitor device (¶0146 – note the supplying of power to the circuit is required for the device to functon).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi as applied to Claim 1 above.
Regarding Claim 3, Yamaguchi teaches Claim 1 as indicated above. Yamaguchi does not specifically teach the resistor has a resistance in a range from 0.01 mΩ to 1 mΩ. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to optimize the resistance of the resistor unit, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Omae et al. (US Patent Application Publication No. 2024/0243030)
Noh (US Patent Application Publication No. 2008/0175082)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891