DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election, without traverse, of Invention I directed to device, Claims 1-12, in the Response to Restriction Requirements filed 04/13/26 has been acknowledged.
Together with the Response, Applicant submitted some amended paragraphs of the specification, a replacement for Fig. 7A, and amended Claim 7 (without introduction of a new matter).
Status of Claims
Claims 13-22 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-12 are examined on merits herein.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 recites: “the conductive gate contact is in contact with one of the source select line, the plurality of word lines, and the drain select line”. Examiner suggests amending the recitation for a better clarity as shown below: “the conductive gate contact is in contact with one of the source select line, the drain select line or one word line of the plurality of word lines”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9-10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sano et al. (US 2022/0189872).
In re Claim 1, Sano teaches semiconductor memory device (Abstract) comprising Figs. 47A and 47B and Annotated Fig. 47B:
Annotated Fig. 47B
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a stack structure including (paragraphs 0098-0099) a cell array region 100 and a contact region 200 extending in a first direction (being a horizontal direction) from the cell array region 100;
a cell plug 58 (paragraph 156) penetrating the cell array region of the stack structure;
a conductive gate contact 86 (paragraph 0196) penetrating the contact region 200 of the stack structure; and
a plurality of first support structures 220-1 (220-1 in Annotated Fig. 47B are 220, but contacting a perimeter of the conductive gate contact 86, paragraph 0213) bordering a perimeter of the conductive gate contact 86 and disposed to be spaced apart from the center of the conductive gate contact at a first distance d1 (as in Annotated Fig. 47B).
In re Claim 2, Sano teaches the semiconductor memory device of Claim 1 as cited above, wherein the plurality of first support structures 220-1 (of Annotated Fig. 47B) are disposed in substantially a circle to be spaced apart from the center of the conductive gate contact 86 at the first distance d1.
In re Claim 3, Sano teaches the semiconductor memory device of Claim 1, wherein
the stack structure includes (see Figs. 1A-1C, 25) a source select line 118 (paragraph 0092), a plurality of word lines 146, 246 (paragraph 0185, except for two upper lines 246), and a drain select line (the upper line 246, paragraph 0188 – as a drain select gate), which are stacked to be spaced apart from each other in a length direction of the cell plug (e.g., in a height direction of the cell plug), and wherein
the conductive gate contact – as one of gate contacts 86 (Fig. 47A) is in contact with one of the source select line, the plurality of word lines, and the drain select line.
In re Claim 4, Sano teaches the semiconductor memory device of Claim 1,
wherein (Figs. 47A, 47B) each of the cell plug 58 and the plurality of first support structures 20 (as in Figs. 16, paragraph 0157, or 220, as in Figs. 47, paragraph 0215) includes (Figs. 16 show details better): a channel layer 60 (paragraph 0148); and a memory layer 50 (paragraph 0150) between the channel layer 60 and the stack structure.
In re Claim 6, Sano teaches the semiconductor memory device of Claim 1, further comprising (Annotated Fig. 47B) a plurality of second support structures 220 (connected by imaginary, but shown lines in Annotated Fig. 47B) bordering a perimeter of the conductive gate contact 86 and disposed to be spaced apart from the center of the conductive gate contact 86 at a second distance d2 greater than the first distance d1.
In re Claim 7, Sano teaches the semiconductor memory device of Claim 6 as cited above, wherein (Annotated Fig. 47B) the plurality of second support structures 220 are disposed in substantially a circle to be spaced apart from the center of the conductive gate contact 86 at the second distance d2.
In re Claim 9, Sano teaches the semiconductor memory device of Claim 1 as cited above and further comprising (Fig. 47A and Annotated Fig. 47B-1) a plurality of main support structure MSS penetrating the contact region of the stack structure.
Annotated Fig. 47B-1
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In re Claim 10, Sano teaches the semiconductor memory device of Claim 9 as cited above, wherein (Annotated Fig. 47B-1) the plurality of main support structure MSS are arranged in a sig-zag shape.
In re Claim 12, Sano teaches the semiconductor memory device of Claim 1 as cited above, wherein the stack structure (of Fig. 47A) includes a plurality of interlayer insulating layers 132, 232 (paragraph 0141) and a plurality of conductive layers 146, 246 (paragraph 0185), which are alternately stacked in a length direction of the cell plug 58.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sano in view of Watanabe (US 2022/0415907).
In re Claim 5, Sano teaches the semiconductor memory device of Claim 1 as cited above, including the first support structures penetrating the stack structure, but does not teach that at least one of the plurality of first support structures is formed of an insulating material filling a support hole penetrating the stack structure.
Watanabe teaches (Figs. 33C and 34C) that a first support structure 24/22 is formed of an insulating material (paragraphs 0191, 0174, 0173 – e.g., when 24 and 22 are formed from a same dielectric material) filling a support hole 117 (Fig. 21A, paragraph 0172) penetrating a stack structure.
Sano and Watanabe teach analogous arts directed to three-dimensional memories comprised support structures in a contact region, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sano device in view of the Watanabe device, since they are from the same field of endeavor, and Watanabe created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sano structure by creating at least one of its first support structures from an insulating material filling a support hole penetrating the stack structure, when the manufacturer prefers creating the support structure from the insulating material: see MPEP 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).. see also Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988)
Allowable Subject Matter
Claims 8 and 11 contain allowable subject matter; these claims are objected by the current Office Action as being dependent on rejected base claims, but would be allowed if amended to incorporate all imitations of the base claim and all intervening claims.
Reason for Identification Allowable Subject Matter
Re Claim 8: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 8 as: “a number of the second support structures is greater than or equal to a number of the first support structures”, in combination with other limitations of Claim 8 and with combination of limitations of Claims 6 and 1, on which Claim 8 depends.
Re Claim 11: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitations of Claim 11 as: “of main support structures includes:
n first main support structures constituting a first column, the n first main support
structures being arranged in a line in the first direction; (n-1) second main support structures constituting a second column adjacent to the first column in a second direction intersecting the first direction, the (n-1) second main support structures being arranged in a line in the first direction; and a plurality of third main support structures adjacent to the plurality of first support structures”, in combination with other limitations of the claim and in combination with all limitations of Claims 9 and 1, on which Claim 11 depends.
The prior arts of record, in addition to the prior arts cited by the current Office Action, also include: Lee et al. (US 2022/0199767), Kubo et al. (US 2022/0328413), Tanaka et al. (US 2022/0005824), Park et al. (US 2020/0185400), Ariyoshi (US 2018/0261613), and Shin et al. (US 9,564,451).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 05/22/26
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