Prosecution Insights
Last updated: October 04, 2026
Application No. 18/519,056

APPARATUS AND METHOD FOR FLIP CHIP LASER BONDING

Non-Final OA §103
Filed
Nov 26, 2023
Priority
Nov 29, 2022 — RE 10-2022-0162451
Examiner
WOLDEGEORGIS, ERMIAS T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Protec Co. Ltd.
OA Round
2 (Non-Final)
71%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
542 granted / 764 resolved
+2.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
47 currently pending
Career history
805
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 764 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Claims 10-13 have been cancelled; Claims 1, 7, and 14 have been amended; and claims 1-9 and 14 are currently pending. Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 2021/0335749 A1, hereinafter “AHN”) in view of Park et al. (US 2021/0398936 A1, hereinafter “Park”) and Yoshimoto et al. (US 2007/0215673 A1, hereinafter “Yoshimoto”). In regards to claim 1, Ahn discloses (see, for example, Figs. 1, 2, 4 and 5) a flip-chip laser bonding method of bonding a flip-chip type semiconductor chip to a substrate using a laser light (see, for example, Abstract), the method comprising: a step (a) of adsorbing, holding, and supporting a lower surface of a substrate by a substrate support member (See, for example, Par [0039] ‘…suppling unit 110 supplies the substrate to the fixing unit…”); a step (b) of holding and supporting an upper surface of the semiconductor chip by a chip support member (See, for example, Pars [0035] and [0043]); a step (c) of transferring the chip support member relative to the substrate support member such that a position of the semiconductor chip is aligned with respect to the substrate and bringing the semiconductor chip to be in contact with the substrate by a chip transfer unit (See, for example, Par [0040]-[0042]); and a step (d) of bonding the semiconductor chip to the substrate by irradiating the lower surface of the substrate, which is being in contact with the semiconductor chip and supported on the substrate support member, with the laser light by a laser head (a laser unit 200 including a laser head 210 which radiates a laser beam onto the substrate fixed on the fixing unit 120 to transfer energy, whereby the solder bumps of the semiconductor chips are instantaneously melted and solidified and the semiconductor chips are bonded to the substrate, and a laser transport unit 200 which moves the laser head 210 in the vertical and horizontal directions; See Pars [0016] and [0021]) feedbac Ahn further teaches the substrate, which is being in contact with the semiconductor chip (the semiconductor chips having flux-coated solder bumps thereunder are temporarily bonded to the substrate and are kept in position relative to the substrate by the flux; and a pressing unit 350 raises or lowers one of the mask mounting unit 300 and the fixing unit 120 with respect to the other so that the transmission portions 440 press the semiconductor chips flat against the substrate while the laser head 210 radiates the laser beam, whereby the semiconductor chips are prevented from being warped or bent; See Par [0018], [0021]-[0023], and [0045]) and supported on the substrate support member (a fixing unit 120 which receives the substrate from a supply unit 110 and fixes the substrate by adsorbing the lower surface thereof, the substrate remaining fixed on the fixing unit 120 while the laser head 210 radiates the laser beam; See for example, Pars [0020] and [0039]). wherein each of the steps (a), (b), (c), and (d) are performed using a control unit configured to control operations of the substrate support member, the chip support member, the chip transfer unit, and the laser head (a control unit 500 which controls the operations of the supply unit 110, fixing unit 120, the laser unit 200 and the discharge unit 130; the control unit 500 operating the laser unit 200 such that the laser head 210 radiates a laser beam while sequentially moving above the semiconductor chips of the substrate fixed on the fixing unit 120, identifying the positions of the semiconductor chips using images received from an inspection camera 230, and feedback controlling the operation of the laser head 210 using measurements received from an infrared camera 240; See for example, Pars [0021], [0027]and [0053]). However, Ahn is silent about irradiating the lower surface of the substrate. Park while disclosing a laser bonded device teaches (See, Figs. 2A, 3A-3C, 5A-5B and 6A) irradiating the lower surface of the substrate (In the example shown in FIG. 2A, laser-assisted-bonding (LAB) tool 15 can comprise laser source 151, stage block (or base chuck) 152, and window 153. Par [0029]; LAB tool 15 can be positioned below semiconductor device 10 and stage block 152 can be spaced apart from laser source 151 and can be positioned above laser source 151. laser beams 151A are irradiated from laser source 151, and heat can be applied or transferred to interconnects 121 or 131 through window 153 and substrate 11 and to melt or reflow interconnects 121 or 131 and bond electronic components 12 or 13 to substrate 11 and laser beam 151A can be applied to interconnect 121 or 131 from a second side of substrate 11 opposite to the first side. See Pars [0039], [0042] and [0043]). It further teaches that the lower surface so irradiated is “supported on the substrate support member” (window 153 can be coupled to stage block 152. Window 153 can support semiconductor device 10. Par [0040]; Window 153 can be made of a material capable of permitting passage of laser beams. In some examples, window 153 can be made of quartz or glass … window 153 can comprise a material exhibiting any amount of light transmissivity to allow light at the desired wavelength to pass through, for example at or near the wavelength of laser beams 151A. In some examples, the transmittance of window 153 for laser beams can be about 90% or greater to facilitate the LAB process. Window 153 can comprise one or more vacuum holes therethrough to allow the application of vacuum to semiconductor device 30. Lab tool 15 can include a vacuum mechanism to apply vacuum through the vacuum holes of window 153 to force semiconductor device 30 including substrate 11 against window 153 during heating to prevent warpage of substrate 11. Pars [0041] and [0054]); the step (c) comprises: a first process in which the control unit controls the chip transfer unit to adjust a height of the chip support member, bringing the semiconductor chip into contact with the substrate (See for example, Pars [0056] and [0057]; Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified Ahn to irradiate the lower surface of the substrate as taught by Park because applying the heat directly to the interconnects while maintaining the temperature of the substrate and of the electronic component lower than that of the heated interconnects, thereby avoiding undue heating or damage to the dielectric and conductive structures of the substrate and preventing warpage of the semiconductor chip. Ahn as modified by Park is silent about a control unit configured to control operations of … the chip support member, the chip transfer unit. Yoshimoto while disclosing teaches a control unit configured to control operations of … the chip support member, the chip transfer unit (As a pressure load (whole bonding load) applied to bond the connection terminals 1A of the substrate 1 to the bumps 6A of the electronic component 6, a reference pressure and the descending speed of the bonding tool 7 are set by the control unit 21 (e.g., a microcomputer). In this embodiment, pressure values detected by the load sensors 5A to 5D are used to set the upper and lower thresholds for a pressing force on each of the load sensors 5A to 5D. See for example, Par [0060], [0061]). a second process in which the control unit operates the chip transfer unit to lower the chip support member after the step (d) started to perform (See, for example, Pars [0049] and [0061]); a third process in which the control unit operates the chip transfer unit to maintain the height of the chip support member after the second process is performed (See, for example, Pars [0049], . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the combination of Ahn and Park with the control unit driven height adjustment of the chip support member as taught by Yoshimoto because maintaining the load applied to the semiconductor chip at a set reference pressure throughout the bonding operation, thereby preventing the connection defects that arise at fine bump pitch from excessively crushed bumps, from variation in bump height, and from non-parallelism between the bonding tool and the substrate. In regards to claim 2-4, AHN as modified above discloses discloses (See, for example, Fig. 2B, Park) wherein the step (a) is performed using the substrate support member comprising a transmission portion comprising a transparent material to transmit the laser light emitted from the laser head in the step (d) to the substrate (11/153, “…heat can be applied to interconnects 121 or 131. In some examples, such heat can be applied to interconnects 121 or 131 while maintaining the temperature of substrate 11 lower than the temperature of heated interconnects 121 or 131….”, See, for example, Pars [0041]- [0042]); wherein the step (a) is performed using the substrate support member comprising the transmission portion comprising quartz (See, for example, Par [0041); and wherein the step (a) is performed using the substrate support member comprising the transmission portion comprising a porous resin (substrate 11 can be a re-distribution layer (“RDL”) substrate. In some examples, RDL substrates can comprise one or more conductive redistribution layers and one or more dielectric layers that can be formed layer by layer over an electronic device to which the RDL substrate is to be electrically coupled. … The dielectric layers can be made from photo-definable organic dielectric materials such as, for example, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO)…”, See, for example, Par [0027]; also, “…Laser beams 151A can transfer or induce heat to interconnects, 121, 131, 141…”, See, for example, Par [0066]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify AHN by Park because this would help bond semiconductor device to the substrate in an efficient/effective manner. In regards to claim 9, Park discloses (See, for example, Fig. 1) the semiconductor chip is bonded to the substrate using one of a solder ball and a copper pillar as a solder bump (See, for example, Par [0016]). Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over AHN in view of Park and Yoshimoto, as applied to claim 1 above, and further in view of KIM et al. (US 2018/0102340 A1, hereinafter “Kim”). In regards to claims 5-8, AHN discloses all limitations of claim 1 above except that the step (b) comprises holding and supporting the semiconductor chip by adsorbing the upper surface of the semiconductor chip by the chip support member; the step (b) is performed using the chip support member comprising a tilting unit configured to contact the upper surface of the semiconductor chip and tilt in accordance with an inclination of the upper surface of the semiconductor chip to adsorb and support the semiconductor chip; wherein the step (b) comprises supporting the semiconductor chip while maintaining an angle of the tilt in accordance with the inclination of the upper surface of the semiconductor chip by the tilting unit, and the step (c) comprises transferring the chip support member while maintaining the angle of the tilt of the semiconductor chip tilted in the step (b); wherein the step (b) is performed using the chip support member comprising the tilting unit comprising a contact portion configured to contact and support the upper surface of the semiconductor chip and a fixed portion tiltably supporting the contact portion, wherein the fixed portion and the contact portion are configured such that surfaces thereof facing each other are curved to allow relative tilting, and an angle of the contact portion with respect to the fixed portion is maintained by pneumatic pressure. Kim while disclosing a bonding head teaches (See, for example, Fig. 4-8) that the step (b) comprises holding and supporting the semiconductor chip (C) by adsorbing the upper surface of the semiconductor chip (C) by the chip support member (124); the step (b) is performed using the chip support member (124) comprising a tilting unit (“ the second correcting block 144… collet 124 may be free to move with respect to the second correcting block 144.” , See Pars [0033]-[0034]) configured to contact the upper surface of the semiconductor chip (C) and tilt in accordance with an inclination of the upper surface of the semiconductor chip (C) to adsorb and support the semiconductor chip (C); wherein the step (b) comprises supporting the semiconductor chip (C) while maintaining an angle of the tilt in accordance with the inclination of the upper surface of the semiconductor chip by the tilting unit (See, for example, Fig. 6), and the step (c) comprises transferring the chip support member while maintaining the angle of the tilt of the semiconductor chip tilted in the step (b) (See, for example, Figs. 5 and 6); wherein the step (b) is performed using the chip support member comprising the tilting unit (124) comprising a contact portion configured to contact and support the upper surface of the semiconductor chip (C) and a fixed portion tiltably supporting the contact portion (See, Figs. 7/8), wherein the fixed portion and the contact portion are configured such that surfaces thereof facing each other (between 142 and 144) are curved to allow relative tilting, and an angle of the contact portion with respect to the fixed portion is maintained by pneumatic pressure (See, for example, Pars [0035]-[0036]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify AHN by Kim because this would help reduce failures in the bonding process and bonding time. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over AHN in view of Park and Yoshimoto as applied to claim 1, and further in view of Seok et. al. (US 2016/0079199 A1, hereinafter “Seok”). In regards to claim 14, AHN as modified above discloses all limitations of claim 11 except that a step (e) of capturing an image of the upper surface of the substrate placed on the substrate support member by a substrate camera; and a step (f) of capturing an image of the lower surface of the semiconductor chip supported on the chip support member by a chip camera, wherein the step (c) comprises adjusting a position and a direction of the semiconductor chip with respect to the substrate using the images captured in the steps (e) and (f). Seok while disclosing apparatus for bonding semiconductor chips teaches (See, for example, Figs. 1) further comprising: a step (e) of capturing an image of the upper surface of the substrate placed on the substrate support member by a substrate camera (“…a second camera to capture an image of the substrate and to obtain positional information regarding the substrate…”, See, for example, Abstract); and a step (f) of capturing an image of the lower surface of the semiconductor chip supported on the chip support member by a chip camera (“…first camera to capture an image of the semiconductor chip and to obtain positional information regarding the semiconductor chip…”, See, for example, Abstract) , wherein the step (c) comprises adjusting a position and a direction of the semiconductor chip with respect to the substrate using the images captured in the steps (e) and (f) (“…The bonding controller may calculate position precision of the correction chip on the correction substrate in accordance with the fiduciary marks on the correction chip and the correction substrate as captured by the first and second cameras, respectively.”, See, for example, Pars [0016] and [0025]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify AHN further by Seok because this would help enhance precision. Response to Arguments Applicant’s arguments, see page 9, filed on 04/23/2026, with respect to claim 1 have been fully considered and are persuasive. The rejection of claim 1 has been withdrawn. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Nov 26, 2023
Application Filed
Jan 27, 2026
Non-Final Rejection mailed — §103
Apr 23, 2026
Response Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
71%
Grant Probability
83%
With Interview (+11.9%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 764 resolved cases by this examiner. Grant probability derived from career allowance rate.

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