DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, and 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chidambaram et al. (US 20050012396).
Regarding claim 1, Chidambaram teaches
An electronic device, comprising:
a power up circuit (Fig. 1 (input conditioning – 16 and power supply controller - 17)), configured to generate a power up signal according to whether a power voltage reaches a predetermined voltage level; ([0034-35], “The controller 17 then controls the power supplies 10 to 15 for producing respective supply voltages on rails V0 to V5 for electrical circuits on the circuit card. This control includes monitoring of the input voltage Vin and the output voltages of the controlled power supplies 10 to 15, and sequencing of the power supplies on power-up … each of the power supplies or converters 10, 11, and 15 is an isolating switch mode power supply (SMPS), also referred to as a DC or DC-to-DC converter or a brick, whose source voltage is the input voltage Vin conditioned by the unit 16.” And [0007], “ enabling of each individual controlled power supply on power-up of the circuit card can be dependent upon the input voltage, or upon a monitored output voltage of a prior-enabled power supply, exceeding a threshold voltage.”)
a delay circuit ([0034], “start-up delay timer(s)”), configured to provide a plurality of enable signals by delaying the power up signal with different delay times; and ([0039], “the controller 17 initially (for example on determining that the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20. When this output voltage exceeds a specified voltage threshold VT0, a start-up delay timer for the power supply 11, which is specified as being next in this power-up sequence, is started to time a specified period T1, on the expiry of which the controller 17 enables this power supply 11 so that its output voltage rises as shown by the line 21. When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22.”)
a plurality of power supply circuits (Fig. 1, (power supplies – 10, 11, and 15)), directly coupled to receive the same power voltage (Fig. 1, [0035], “each of the power supplies or converters 10, 11, and 15 is an isolating switch mode power supply (SMPS) … whose source voltage is the input voltage Vin conditioned by the unit 16.”) and configured to be respectively activated by the plurality of enable signals to convert the same power voltage into a plurality of power supply voltages (Fig. 2, Voltages V0, V1, and V2). (Figs. 1-2, and 6-11, [0039], “the controller 17 initially (for example on determining that the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20. When this output voltage exceeds a specified voltage threshold VT0, a start-up delay timer for the power supply 11, which is specified as being next in this power-up sequence, is started to time a specified period T1, on the expiry of which the controller 17 enables this power supply 11 so that its output voltage rises as shown by the line 21. When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22.” Where the same voltage source is interpreted as Vin after input conditioning. Additionally, as shown by Fig. 2, Voltages V0, V1, and V2 are all the plurality of power supply voltages)
Regarding claim 2, Chidambaram teaches wherein the power up circuit is configured to switch the power up signal to an enabling voltage level when the power up circuit senses that the power voltage rises to be greater than a predetermined voltage level. ([0039], “the controller 17 initially (for example on determining that the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20.”)
Regarding claim 4, Chidambaram teaches wherein each of the power supply circuit is activated by the corresponding enable signal to convert the power voltage to a corresponding one of power supply voltage. ([0039], “the controller 17 initially (for example on determining that the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20. When this output voltage exceeds a specified voltage threshold VT0, a start-up delay timer for the power supply 11, which is specified as being next in this power-up sequence, is started to time a specified period T1, on the expiry of which the controller 17 enables this power supply 11 so that its output voltage rises as shown by the line 21. When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22.”)
Regarding claim 5, Chidambaram teaches wherein at least one of the power supply circuits is a low drop-out (LDO) circuit or a DC-DC converter. (Fig. 1 (LDO – 14), [0035], “The power supply 14 is a non-isolating linear voltage regulator, which typically has a low drop out voltage and accordingly is also referred to as an LDO.”)
As to claim 11, Chidambaram teaches these claims according to the reasoning provided in claim 1.
As to claim 12, Chidambaram teaches these claims according to the reasoning provided in claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram in view of Zwerg (US 20230315142)
Regarding claim 3, Chidambaram teaches using threshold voltages to power up multiple power supplies.
Zwerg teaches wherein the predetermined voltage level is selected from a range between 0.5V-0.9V. ([0023], “The example POR circuitry 200 of FIG. 2 is threshold voltage-based circuitry with a threshold that can vary from, for example, 0.9 V”)
Chidambaram and Zwerg are analogous art. Zwerg is cited to teach a similar concept of powering up a system safely. Chidambaram teaches using threshold to power up multiple power supplies but does not specify the voltage level. Zwerg teaches that the threshold for powering on could between 0.9V-1.3V. Both Chidambaram and Zwerg teach powering up of an electronic device and therefore, using a threshold voltage of 0.9 V would have a reasonable expectation of success. Based on Zwerg and the KSR rationale of "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use a power up voltage threshold of 0.9V.
As to claims 13, Chidambaram and Zwerg teach these claims according to the reasoning provided in claim 3.
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram in view of Gou (US 5451894).
Regarding claim 6, Chidambaram teaches
between the power up circuit and the corresponding power supply circuit. ([0039], “As shown in FIG. 2, the controller 17 initially (for example on determining that the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20. When this output voltage exceeds a specified voltage threshold VT0, a start-up delay timer for the power supply 11, which is specified as being next in this power-up sequence, is started to time a specified period T1, on the expiry of which the controller 17 enables this power supply 11 so that its output voltage rises as shown by the line 21. When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22.”)
Chidambaram teaches using a timer to provide delays for powering up power supply circuits but does not teach specifics of the circuitry for the delays.
Gou teaches wherein the delay circuit comprises a plurality of delay chains (Fig. 2, (D1-DN)), and each of the delay chain comprises at least one unit delay cell (Fig. 2 (inverters – 501)) coupled in series between the power up circuit and the corresponding power supply circuit. (Fig. 2)
Chidambaram teaches using a delay circuit to control the powering up of power supplies in an electronic device where different power supplies receive different delays for powering up. Gou is cited to teach a similar concept of using a delay circuit in an electronic device. Gou teaches that the delay circuits may use inverters as unit delay, and that there are multiple taps to select different delays which may be used for different enable signals. Gou teaches a flexible delay circuit which can delay multiple devices in an efficient way with the flexibility of choosing from a range of delay times. Additionally, because both Chidambaram and Gou describe delay circuits substituting Chidambaram’s delay circuit for Gou’s delay circuit would obtain predictable results. Based on Gou and the KSR rational of simple substitution of one known element for another to obtain predictable results, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use the delay circuit of Gou.
Regarding claim 7, Gou teaches wherein each of the unit delay cell is a RC delay cell, a buffer, an inverter, or a flip-flop. (Fig. 2 (inverters – 501))
Chidambaram teaches using a delay circuit to control the powering up of power supplies in an electronic device where different power supplies receive different delays for powering up. Gou is cited to teach a similar concept of using a delay circuit in an electronic device. Gou teaches that the delay circuits may use inverters as unit delay, and that there are multiple taps to select different delays which may be used for different enable signals. Gou teaches a flexible delay circuit which can delay multiple devices in an efficient way with the flexibility of choosing from a range of delay times. Additionally, because both Chidambaram and Gou describe delay circuits substituting Chidambaram’s delay circuit for Gou’s delay circuit would obtain predictable results. Based on Gou and the KSR rational of simple substitution of one known element for another to obtain predictable results, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use the delay circuit of Gou.
Regarding claim 8, Gou teaches wherein each of the unit delay cell is the buffer or the inverter (Fig. 2 (inverters – 501)), and sizes of the unit delay cells are different. (Fig. 2)
Chidambaram teaches using a delay circuit to control the powering up of power supplies in an electronic device where different power supplies receive different delays for powering up. Gou is cited to teach a similar concept of using a delay circuit in an electronic device. Gou teaches that the delay circuits may use inverters as unit delay, and that there are multiple taps to select different delays which may be used for different enable signals. Gou teaches a flexible delay circuit which can delay multiple devices in an efficient way with the flexibility of choosing from a range of delay times. Additionally, because both Chidambaram and Gou describe delay circuits substituting Chidambaram’s delay circuit for Gou’s delay circuit would obtain predictable results. Based on Gou and the KSR rational of simple substitution of one known element for another to obtain predictable results, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use the delay circuit of Gou.
Regarding claim 9, Gou teaches wherein each of the unit delay cell provides a same unit delay time, and the plurality of delay chains comprise different numbers of the unit delay cells. (Fig. 2)
Chidambaram teaches using a delay circuit to control the powering up of power supplies in an electronic device where different power supplies receive different delays for powering up. Gou is cited to teach a similar concept of using a delay circuit in an electronic device. Gou teaches that the delay circuits may use inverters as unit delay, and that there are multiple taps to select different delays which may be used for different enable signals. Gou teaches a flexible delay circuit which can delay multiple devices in an efficient way with the flexibility of choosing from a range of delay times. Additionally, because both Chidambaram and Gou describe delay circuits substituting Chidambaram’s delay circuit for Gou’s delay circuit would obtain predictable results. Based on Gou and the KSR rational of simple substitution of one known element for another to obtain predictable results, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use the delay circuit of Gou.
Regarding claim 10, Chidambaram teaches wherein the delay circuit comprises a delay chain coupled to the power up circuit, ([0039], “When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22”)
Chidambaram teaches using a timer to provide delays for powering up power supply circuits but does not teach specifics of the circuitry for the delays.
Gou teaches
the delay chain comprises a plurality of unit delay cells coupled in series (Fig. 2 (inverters – 501)), and the enable signals are outputted by different stages of the unit delay cells in the delay chain. (Fig. 2)
Chidambaram teaches using a delay circuit to control the powering up of power supplies in an electronic device where different power supplies receive different delays for powering up. Gou is cited to teach a similar concept of using a delay circuit in an electronic device. Gou teaches that the delay circuits may use inverters as unit delay, and that there are multiple taps to select different delays which may be used for different enable signals. Gou teaches a flexible delay circuit which can delay multiple devices in an efficient way with the flexibility of choosing from a range of delay times. Additionally, because both Chidambaram and Gou describe delay circuits substituting Chidambaram’s delay circuit for Gou’s delay circuit would obtain predictable results. Based on Gou and the KSR rational of simple substitution of one known element for another to obtain predictable results, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Chidambaram to use the delay circuit of Gou.
Response to Arguments
Applicant's arguments filed 6/26,2025 have been fully considered but they are not persuasive. The Applicant’s representative argues that the limitations, “a delay circuit configured to provide a plurality of enable signals by delaying the power up signal with different delay times;” and “a plurality of power supply circuits directly coupled to receive the same power voltage and configured to be respectively activated by the plurality of enable signals to convert the same power voltage into a plurality of power supply voltages.” The Examiner respectfully disagrees. Regarding the limitation, “a delay circuit configured to provide a plurality of enable signals by delaying the power up signal with different delay times;”, the Applicant argues the power supplies of Chidambaram, do not teach the power supply circuits being directly coupled to receive the same power supply voltage and convert the power voltage into power supply voltages. As shown in Fig. 1 of Chidambaram, there is a direct connection from Vin through input conditioning to power supply blocks 10, 11, and 15 (i.e. they all receive the same voltage) through a direct connection. Additionally, as shown in Figs. 1 and 2, the output voltages of power supplies 10, 11, and 15 are respectfully, V0, V1, and V5 and they each supply different voltages (i.e. “the plurality of power supply voltages”). The Applicant also argues the power supplies of Chidambaram are not directly coupled to receive different power voltages. This argument is confusing because according to the claim limitations state that the “a plurality of power supply circuits directly coupled to receive the same power voltage” not different voltages. Then, the power supplies are to supply “to convert the same power voltage into a plurality of power supply voltages” which as shown by Fig. 2 (V0, V1, and V2) they do. Therefore, these arguments are not persuasive.
As well, the Applicant’s representative argues that the claim language requires the delay circuits to receive the same power up signal and generate the enable signals with different delays. Each delay signal is initiated by the power up signal rising above a threshold as taught by Chidambaram. Paragraph [0039] teaches this concept “the input voltage Vin has exceeded a specified threshold voltage for a specified time period) enables the power supply 10, and its output voltage rises as shown by the line 20. When this output voltage exceeds a specified voltage threshold VT0, a start-up delay timer for the power supply 11, which is specified as being next in this power-up sequence, is started to time a specified period T1, on the expiry of which the controller 17 enables this power supply 11 so that its output voltage rises as shown by the line 21. When this output voltage exceeds a specified voltage threshold VT1, a start-up delay timer for the power supply 12, which is specified as being next in this power-up sequence, is started to time a specified period T2, on the expiry of which the controller 17 enables this power supply 12 so that its output voltage rises as shown by the line 22.”. The above paragraph describes the first voltage Vin rises above a threshold and asserts an enable (“the same power up signal”). Then, the power supply (10) is enabled and the V0 rail rises above a voltage threshold VT0 and a delay time T1 is initiated. This event causes the power supply (11) for the V1 rail to be enabled. In other words, a chain of events from the first threshold voltage Vin and time period to a rise above threshold VT0 rise of voltage V0 and a delay time T1, then causes the power supply (11) to be enabled after a second time period T2 where “the same power up signal” has initiated enabling the voltage V2 at the beginning of the chain of events. This type of cycle continues to enable more voltages. Therefore, the same power up signal plus differing delay times are responsible for enabling different voltages. Therefore, the Applicant’s arguments are not persuasive and the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 October 6, 2025
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176