DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of species 2 as shown in fig. 4 (claims 1-20 readable thereon) in the reply filed on 4/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2021/0335763; hereinafter “Chen”).
Re claim 1: Chen teaches (e.g. figs. 4A, 9A, and labeled fig. 9A below) a display panel, comprising: a drive control circuit layer (layer that consists of TFTs 420, 430, 440”; e.g. paragraph 79; hereinafter “DCCL”); micro light-emitting elements (light emitting units 300; e.g. paragraph 67), disposed on the drive control circuit layer (DCCL) and electrically connected (electrical traces connect 300 to DCCL) to the drive control circuit layer (DCCL); an insulation layer (element labeled “IL” in the labeled figure below), disposed on a side (bottom side of DCCL) of the drive control circuit layer (DCCL) facing away from the micro light-emitting elements (300); a fanout wiring layer (element labeled “FOWL” in the labeled figure below), disposed in the insulation layer (IL) and penetrating through the insulation layer (IL), wherein the fanout wiring layer (FOWL) is electrically connected (FOWL is connected through 440f and GND or 440” to 300) to the micro light-emitting elements (300) and the drive control circuit layer (DCCL) individually; a patterned planarization layer (element labeled “PPL” in the labeled figure below), disposed on a side (bottom side of IL) of the insulation layer (IL) facing away from the drive control circuit layer (DCCL); and a bonding wire layer (element labeled “BWL” in the labeled figure below), disposed in through-holes of the patterned planarization layer (PPL) to electrically connect the fanout wiring layer (FOWL), wherein the bonding wire layer (BWL) is configured to externally connect a panel driver circuit (signal reference wires 500).
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Re claim 3: Chen teaches the display panel as claimed in claim 1, wherein the drive control circuit layer (DCCL) comprises: a pixel driving circuit layer (440”), disposed on a side (top side of IL) of the insulation layer (IL) facing away from the patterned planarization layer (PPL), wherein the pixel driving circuit layer (440”) comprises sub-pixel driving circuits (SPDC) electrically connected to the micro light-emitting elements (300) respectively; and a second planarization layer (element labeled “2PL” in the labeled figure above), disposed on a side (top side of 440”) of the pixel driving circuit layer (440”) facing away from the insulation layer (IL), wherein the second planarization layer (2PL) comprises first contact holes (holes for SPDC) arranged corresponding to the sub-pixel driving circuits (SPDC) in a one-to-one manner and penetrating through the second planarization layer (2PL), the first contact holes (holes for SPDC) have respective first connection metal layers (metal layers of SPDC) disposed therein, and the micro light-emitting elements (300) are electrically connected to the sub-pixel driving circuits (SPDC) through the first connection metal layers (metal layers of SPDC) respectively.
Re claim 4: Chen teaches the display panel as claimed in claim 3, wherein each of the micro light-emitting elements (300) comprises a first electrode (450-1) and a second electrode (451f-1), and the first electrode (450-1) is electrically connected to a corresponding one of the sub-pixel driving circuit (SPDC) through the first connection metal layer (metal layers of SPDC); wherein the display panel is further disposed with second contact holes (holes for 480f) penetrating through both the second planarization layer (2PL) and the pixel driving circuit layer (440”), the second contact holes (holes for 480f) have respective second connection metal layers (480f) disposed therein, and the second electrode (451f-1) is electrically connected to the fanout wiring layer (FOWL) through the second connection metal layer (480f).
Re claim 5: Chen teaches the display panel as claimed in claim 4, wherein the fanout wiring layer (FOWL) comprises a data drive voltage line (data lines 471; e.g. paragraph 80), a scan voltage line (scan lines 470; e.g. paragraph 80), a constant-current drive voltage line (power supply lines 472; e.g. paragraph 80), and a reference voltage line (signal reference lines 500; e.g. paragraph 80); the data drive voltage line (471), the scan voltage line (470), the constant-current drive voltage line (472), and the reference voltage line (500) are electrically connected to the drive control circuit layer (DCCL) and the micro light-emitting elements (300).
Re claim 6: Chen teaches the display panel as claimed in claim 5, wherein the sub-pixel driving circuit (SPDC) comprises a first thin film transistor (420) and a second thin film transistor (430); the first thin film transistor (420) comprises a first gate (gate above 420; hereinafter “1G”), a first source (left s/d region of 420; hereinafter “1S”), a first drain (right s/d of 420; hereinafter “1D”), and a first active layer (active layer of 420); the second thin film transistor (430) comprises a second gate (gate above TFT 430; hereinafter “2G”), a second source (left s/d region of 430; hereinafter “2S”), a second drain (right s/d region of 430; hereinafter “2D”), and a second active layer (active layer of 430); the first drain is electrically connected (L1) to the second gate (2G), and the first electrode (450-1) is electrically connected to the second drain (2D) through the first connection metal layer (metal layers of SPDC); the first gate (1G) is electrically connected to the scan voltage line (470), the first source (1S) is electrically connected to the data drive voltage line (471), the second source (2S) is electrically connected to the constant-current drive voltage line (472), and the second electrode (451f-1) is electrically connected to the reference voltage line (500) through the second connection metal layer (480f).
Re claim 7: Chen teaches the display panel as claimed in claim 3, wherein the drive control circuit layer (DCCL) further comprises a light-shielding layer (element labeled “LS” above), and the light-shielding layer (LS) is disposed on a side (upper side of 2PL) of the second planarization layer (2PL) facing away from the pixel driving circuit layer (440”) and located between the micro light- emitting elements (300) and the second planarization layer (2PL).
Re claim 8: Chen teaches the display panel as claimed in claim 1, wherein the display panel further comprises a protective layer (PL), and the protective layer (PL) is disposed on a side (bottom side of PPL) of the patterned planarization layer (PPL) facing away from the fanout wiring layer (FOWL) and exposes the bonding wire layer (BWL).
Re claim 9: Chen teaches the display panel as claimed in claim 1, wherein the patterned planarization layer (2PL) is a multi-layered structure formed by an organic material layer and an inorganic material layer (layers of 2PL can be formed of PET and quartz; e.g. paragraph 48).
Claim(s) 14, 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yueh et al. (US PGPub 2020/0118988; hereinafter “Yueh”).
Re claim 14: Yueh teaches (e.g. fig. 7) a display panel, comprising: a drive control circuit layer (layer that consists of TFTs 3 and 1217; e.g. paragraphs 52 and 53; hereinafter “DCCL”), comprising sub-pixel driving circuits (3), wherein the drive control circuit layer (DCCL) is formed therein with first contact holes (contact hole for 34; hereinafter “1CH”) and second contact holes (contact hole for 33; hereinafter “2CH”), the first contact holes (1CH) have respective first connection metal layers (metal layer 34 which connects 3 and 1212; hereinafter “1CML”) disposed therein, and the second contact holes (2CH) have respective second connection metal layers (metal layer 33; hereinafter “2CML”) disposed therein; micro light-emitting elements (display using micro light emitting units 1212; e.g. paragraph 28), disposed on the drive control circuit layer (DCCL), wherein each of the micro light-emitting elements (1212) comprises a first electrode (1212c) and a second electrode (1212d), the first electrodes (1212c) of the micro light-emitting elements (1212) respectively are electrically connected to the sub-pixel driving circuits (3) through the first connection metal layers (1CML) in the respective first contact holes (1CH); an insulation layer (1211), disposed on a side (bottom side of DCCL) of the drive control circuit layer (DCCL) facing away from the micro light-emitting elements (1212); a fanout wiring layer (1211a that connects to 33, as well as to 31, 34, and 1212c; hereinafter “FOWL”), disposed in the insulation layer (1211) and penetrating through the insulation layer (1211) and thus surrounded by the insulation layer (1211), wherein the fanout wiring layer (FOWL) is in direct metal-to-metal contact with (33 and FOWL contact each other) the sub-pixel driving circuits (3) to form electrical connection, and further is electrically connected (through 3) to the second electrodes (1212d) of the micro light-emitting elements (1212) through the second connection metal layers (2CML) in the respective second contact holes (2CH); a patterned planarization layer (1213), disposed on a side of the insulation layer (1211) facing away from the drive control circuit layer (DCCL); and a bonding wire layer (1215), disposed in through-holes (holes in 1213) of the patterned planarization layer (1213), wherein the bonding wire layer (1215) is in direct metal-to-metal contact with the fanout wiring layer (FOWL) to form electrical connection, and the bonding wire layer (1215) is configured to be externally connected with a panel driver circuit (2).
Re claim 16: Yueh teaches the display panel as claimed in claim 14, wherein the fanout wiring layer (FOWL) comprises a data drive voltage line (1215 that connects to 33; hereinafter “DVL”), a scan voltage line (1215 that connects to 31; hereinafter “SVL”), a constant-current drive voltage line (1215 that connects to 23 of 2; hereinafter “CCDVL”), and a reference voltage line (1215’ that connects to 1212c; hereinafter “RVL”); the data drive voltage line (DVL), the scan voltage line (SVL) and the constant-current drive voltage line (CCDVL) are in direct metal-to-metal contact with each of the sub-pixel driving circuits (3); and the reference voltage line (RVL) is electrically connected to the second electrode (1212c) of each of the micro light-emitting elements (1212) through the second connection metal layer (2CML) in the second contact hole (2CH).
Re claim 17: Yueh teaches the display panel as claimed in claim 14, wherein the display panel further comprises a protective layer (protectively layer 116; e.g. paragraph 45), and the protective layer (116) is disposed on a side of the patterned planarization layer (1213) facing away from the fanout wiring layer (FOWL) and exposes the bonding wire layer (1215).
Re claim 18: Chen teaches the display panel as claimed in claim 14, wherein the patterned planarization layer (1213) is a multi-layered structure formed by stacked organic material layers, or stacked inorganic material layers (1213 is one of silicon oxide, resin, or polymer, which are multiple layers of a material; e.g. paragraph 58), or alternately stacked an organic material layer and an inorganic material layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above.
Re claim 2: Chen teaches substantially the entire structure as recited in claim1 except explicitly teaching the display panel wherein the bonding wire layer (BWL) is a thick metal layer with a thickness greater than or equal to 1 micrometre.
The micro-LED of Chen is on the order of approximately 100 microns wide, therefore the bonding wire layer (BWL) would have a thick metal layer with a thickness greater than or equal to 1 micrometre since the drawing shows the BWL thickness to be approximately 10 microns thick.
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, to use the 10 microns thick BWL as implied by the teachings of Chen in order to have the predictable result of using a known thickness of a conductor known to have sufficiently low resistance by having a 10 micron thick layer of metal.
Claim(s) 10-13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 1 and 11, respectively, above, and further in view of Tsai et al. (US PGPub 2019/0373723; hereinafter “Tsai”).
Re claim 10: Chen teaches substantially the entire device of claim 1 except explicitly teaching the display panel, wherein the display panel further comprises a printed circuit board and a chip-on-flex (COF) electrically connected to the printed circuit board, the COF is bonded to the bonding wire layer to thereby drive the micro light-emitting elements through the bonding wire layer and the fanout wiring layer.
Tsai teaches the display panel as claimed in claim 1, wherein the display panel further comprises a printed circuit board (board 60; e.g. paragraph 27) and a chip-on-flex (COF) (70 consists of COF; e.g. paragraph 27; hereinafter “C”) electrically connected to the printed circuit board (60), the COF (C) is bonded to the bonding wire layer (52) to thereby drive the micro light-emitting elements (41) through the bonding wire layer (52 which corresponds to BWL of Chen) and the fanout wiring layer (32 which corresponds to FOWL of Chen).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the COF connection scheme as taught by Tsai in the device of Chen in order to have the predictable result of using a known method of supplying control signals and power/ground to a display which simplifies manufacture and design by using an established well known method.
Re claim 11: Chen teaches substantially the entire structure as recited in claim 1 except explicitly teaching a tiled display screen, comprising: a plurality of display panels tiled together, wherein each of the plurality of display panels is the display panel as claimed in claim 1; at least one conductive connecting member, wherein each the conductive connecting member comprises a first connection end and a second connection end, the first connection end and the second connection end are bonded to the bonding wire layers of adjacent two display panels of the plurality of display panels, respectively; and a panel driver circuit, comprising a printed circuit board and at least one COF electrically connected to the printed circuit board, wherein each the COF is bonded to the bonding wire layer of a target display panel of the plurality of display panels.
Tsai teaches (e.g. figs. 2, 3, and 8) a tiled display screen (tiled electronic device 101; e.g. paragraph 24), comprising: a plurality of display panels (11, 12) tiled together, wherein each of the plurality of display panels (11, 12) is the display panel (tiled display of Tsai which is equivalent to the tiled displays using microLEDs as taught at paragraph 29 of Chen) as claimed in claim 1; at least one conductive connecting member (conductive structure 60; e.g. paragraph 25), wherein each the conductive connecting member (60) comprises a first connection end (right end of 60 connected to 52; hereinafter “1CE”) and a second connection end (left end of 60 connected to 51; hereinafter “2CE”), the first connection end (1CE) and the second connection end (2CE) are bonded to the bonding wire layers (52, 51) of adjacent two display panels (11, 12) of the plurality of display panels (11, 12), respectively; and a panel driver circuit (circuit board 70, 71, 72 which may include a COF; e.g. paragraph 27), comprising a printed circuit board (film of the chip on film COF; e.g. paragraph 27) and at least one COF (chip of the chip on film COF; e.g. paragraph 27) electrically connected to the printed circuit board (film of the chip on film COF; e.g. paragraph 27), wherein each the COF (chip of the chip on film COF; e.g. paragraph 27) is bonded to the bonding wire layer (52, 51) of a target display panel (12) of the plurality of display panels (11, 12).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the COF connection scheme as taught by Tsai in the device of Chen in order to have the predictable result of using a known method of supplying control signals and power/ground to a display which simplifies manufacture and design by using an established well known method.
Re claim 12: Chen in view of Tsai teaches the tiled display screen as claimed in claim 11, wherein the at least one conductive connecting member (60 of Tsai) is a plurality of conductive connecting members (plural 60 shown in fig. 3 of Tsai), the plurality of display panels (11, 12) are divided into a plurality of groups of display panels (11, 12), the display panels (11, 12) in the same group of display panels (11, 12) are sequentially connected through at least one of the plurality of conductive connecting members (60).
Re claim 13: Chen teaches the tiled display screen as claimed in claim 11, wherein the at least one COF (70) is a plurality of COFs (71, 72 as shown in fig. 8), the plurality of display panels (11, 12) are divided into a plurality of groups of display panels (11, 12), and the plurality of COFs (71, 72) are bonded to the bonding wire layers (51, 52) of respective edge-most display panels of the plurality of groups of display panels (11, 12) respectively.
Re claim 15: Chen teaches substantially the entire structure as recited in claim 14 except explicitly teaching the display panel wherein the bonding wire layer is a thick metal layer with a thickness greater than or equal to 1 micrometre.
The micro-LED of Chen is on the order of approximately 100mictons wide, therefore the bonding wire layer (BWL) would have a thick metal layer with a thickness greater than or equal to 1 micrometre since the drawing shows the BWL thickness to be approximately 10 microns thick.
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, to use the 10 microns thick BWL as implied by the teachings of Chen in order to have the predictable result of using a known thickness of a conductor known to have sufficiently low resistance by having a 10 micron thick layer of metal.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tsai et al. (US PGPub 2019/0373723; hereinafter “Tsai”).
Re claim 19: Yueh teaches (e.g. figs. 2 and 7) a tiled display screen (tiled electronic device using micro LEDs; e.g. paragraphs 28, 59), comprising: display panels (electronic modules 12 connected together in a tiled fashion; e.g. paragraph 24 and 28) tiled together, wherein each of the display panels (12) comprises: a drive control circuit layer (layer that consists of TFTs 3 and 1217; e.g. paragraphs 52 and 53; hereinafter “DCCL”), comprising sub-pixel driving circuits (3), wherein the drive control circuit layer (DCCL) is formed therein with first contact holes (contact hole for 34; hereinafter “1CH”) and second contact holes (contact hole for 33; hereinafter “2CH”), the first contact holes (1CH) have respective first connection metal layers (metal layer 34 which connects 3 and 1212; hereinafter “1CML”) disposed therein, and the second contact holes (2CH) have respective second connection metal layers (metal layer 33; hereinafter “2CML”) disposed therein; micro light-emitting elements (microLED chip 1212a; e.g. paragraphs 28 and 50), disposed on the drive control circuit layer (DCCL), wherein a length, a width and a thickness of each of the micro light-emitting elements (1212a) each are less than 100 micrometres (Examiner is taking Official notice that microLEDs have dimensions of below 100 microns), each of the micro light-emitting elements (1212a) comprises a first electrode (1212c) and a second electrode (1212d), the first electrodes (1212c) of the micro light-emitting elements (1212a) respectively are electrically connected to the sub-pixel driving circuits (3) through the first connection metal layers (1CML) in the respective first contact holes (1CH); an insulation layer (1211), disposed on a side (bottom side of DCCL) of the drive control circuit layer (DCCL) facing away from the micro light-emitting elements (1212a); a fanout wiring layer (1211a that connects to 33; hereinafter “FOWL”), disposed in the insulation layer (1211) and penetrating through the insulation layer (1211) and thus encircled by the insulation layer (1211), wherein the fanout wiring layer (FOWL) is in direct metal-to-metal contact with the sub-pixel driving circuits (3) to form electrical connection, and further is electrically connected to the second electrodes (1212d) of the micro light-emitting elements (1212a) through the second connection metal layers (2CML) in the respective second contact holes (2CH); a planarization layer (1213), disposed on a side of the insulation layer (1211) facing away from the drive control circuit layer (DCCL); and a bonding wire layer (1215), disposed in through-holes (holes in 1213) of the patterned planarization layer (1213), wherein the bonding wire layer (1215) is electrically connected to the fanout wiring layer (FOWL), and the bonding wire layer (1215) is configured to be externally connected with a panel driver circuit (2).
Yueh is silent as to explicitly teaching conductive connecting members, wherein each of the conductive connecting members comprises a first connection end and a second connection end, the first connection end and the second connection end are bonded to the bonding wire layers of adjacent two of the display panels, respectively; and a panel driver circuit, comprising a printed circuit board and at least one COF electrically connected to the printed circuit board, wherein each the COF is bonded to the bonding wire layer of an edge-most display panel of the display panels.
Tsai teaches (e.g. figs. 2, 3, and 8) conductive connecting members (conductive structure 60; e.g. paragraph 25), wherein each of the conductive connecting members (60) comprises a first connection end (right end of 60 connected to 52; hereinafter “1CE”) and a second connection end (left end of 60 connected to 51; hereinafter “2CE”), the first connection end (1CE) and the second connection end (2CE) are bonded to the bonding wire layers (52, 51) of adjacent two of the display panels (11, 12), respectively; and a panel driver circuit (circuit board 70, 71, 72 which may include a COF; e.g. paragraph 27), comprising a printed circuit board (film of the chip on film COF; e.g. paragraph 27) and at least one COF (chip of the chip on film COF; e.g. paragraph 27) electrically connected to the printed circuit board (film of the chip on film COF; e.g. paragraph 27), wherein each the COF (chip of the chip on film COF; e.g. paragraph 27) is bonded to the bonding wire layer (52, 51) of an edge-most display panel (12) of the display panels (11, 12).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the COF connection scheme as taught by Tsai in the device of Chen in order to have the predictable result of using a known method of supplying control signals and power/ground to a display which simplifies manufacture and design by using an established well known method.
Re claim 20: Yueh teaches the tiled display screen as claimed in claim 19, wherein the bonding wire layer (1215 of Chen) is a thick metal layer with a thickness greater than or equal to 1 micrometre (micro-LED of Yueh is on the order of approximately 100 microns wide, therefore the bonding wire layer 1215 would have a thick metal layer with a thickness greater than or equal to 1 micrometre since the drawing shows the 1215 thickness to be approximately 10 microns thick); and wherein the fanout wiring layer (FOWL) comprises a data drive voltage line(1215 that connects to 33; hereinafter “DVL”), a scan voltage line (1215 that connects to 31; hereinafter “SVL”), a constant-current drive voltage line (1215 that connects to 23 of 2; hereinafter “CCDVL”), and a reference voltage line (1215’ that connects to 1212c; hereinafter “RVL”); the data drive voltage line (DVL), the scan voltage line (SVL) and the constant-current drive voltage line (CCDVL) are in direct metal-to-metal contact with each of the sub-pixel driving circuits (3); and the reference voltage line (RVL) is electrically connected to the second electrode (1212c) of each of the micro light-emitting elements (1212a) through the second connection metal layer (2CML) in the second contact hole (2CH).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights