DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in this application. Acknowledgement is made of the amendment received 5/25/26 withdrawing claims 10-18.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-9 and 19-20) in the reply filed on 5/25/26 is acknowledged. Claims 10-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Claims 1-9 and 19-20 are examined in this Office action.
Information Disclosure Statement
Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-3, 8 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites the limitation “The inverter of claim 1, wherein the second trace is conductively coupled to the first capacitor terminal via a first via and the second terminal is conductively coupled to the second trace via a second via.” Clarity is obfuscated because one word is used with two meanings in the same phrase. One definition of via (preposition) is “by way of”. Another definition (noun) is “an interconnection”. This means that the phrase “coupled to the first capacitor terminal via a first via” is unclear. It would be clearer to choose a synonym of the preposition via. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite.
Claim 3 depend from rejected claim 2, include all limitations of claim 2 and therefore are rejected for the same reason.
Claim 8 recites the limitation “wherein the first transistor further includes a first drain terminal and the second transistor includes a second drain terminal”. Claim 8 depends on claim 1, however, claim 1 already recites “a first drain terminal and a second drain terminal”. Its unclear if these new first and second drain terminals of claim 8 are the same or different that the first and second drain terminals of claim 1. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite.
Claim 20 recites the limitation “wherein the decoupling capacitor, upper PCB trace and lower PCB trace are electrically isolated from the thermally conductive layer”. Claim 20 depends on claim 19, however, claim 19 does not include an upper PCB trace and lower PCB trace. The recitation lacks antecedent basis. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite.
Allowable Subject Matter
Claims 1, 4-7, 9 and 19 are allowed. Claims 2-3, 8 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter. The closest prior art appears to be Todd et al. (US Patent Application Publication No 2008/0232019) hereinafter referred to as Todd which teaches an inverter device, comprising a first transistor (406), having a first terminal (upper) and a first drain terminal (lower); (as shown in figure 4) a second transistor (410), having a second terminal (upper) and a second drain terminal (lower); (as shown in figure 4) and a decoupling capacitor (402) having a first capacitor terminal conductively coupled to the first drain terminal and a second capacitor terminal conductively coupled to the second terminal
Todd does not teach a printed circuit board having an upper surface, a tower surface and an internal layer disposed between the lower surface and the upper surface; a first transistor (406), disposed on the upper surface, having a first terminal (upper) and a first drain terminal (lower); (as shown in figure 4) a second transistor (410), disposed on the upper surface, having a second terminal (upper) and a second drain terminal (lower); (as shown in figure 4) anda decoupling capacitor (402) having a first capacitor terminal conductively coupled to the first drain terminal via a first trace laminated to the upper surface and a second capacitor terminal conductively coupled to the second terminal via a second trace laminated to the lower surface and the first terminal being conductively coupled to the second drain terminal via a third trace laminated to the upper surface.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Parkhideh (US 11,824,344) is cited for teaching an analogous device that includes many features of claim1 but does not include a printed circuit board.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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