DETAILED ACTION
This office action is in response to the election filed 7/20/2026.
Currently, claims 1-20 are pending.
Election/Restrictions
Applicant’s election without traverse of claims 1-4, 7-8 and 17-20 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitations “a fourth semiconductor chip” and “a fourth molding layer”. These limitations imply that there would also be a third semiconductor chip and a third molding layer. However, there is no mention of a third semiconductor chip or a third molding layer in the claims preceding claim 8. Thus, it is unclear how many chips and molding layers are actually being claimed.
Claim 20 recites the limitations “the first redistribution substrate includes an insulating layer and a wiring pattern in the insulating layer”, “a wiring portion extending onto an upper surface of the insulating layer” and “a width of the via portion narrows toward the upper surface of the first redistribution substrate”. Referencing FIG. 2 and the specification, the via portions of wiring pattern 120 narrow as they move up the page, implying that the upper surface of a layer is the surface that is higher up on the page. However, FIG. 2 shows that the wiring portions do not extend along this surface of the insulating layer. On the contrary, they extend along the bottom surface of the insulating layer. This makes it unclear which surface is the upper surface. The Examiner notes that there is what is likely a metal pattern at the bottom of the connection substrate (connected to via 412), although it is not disclosed in detail. However, it is formed on an upper surface of the upper-most insulation layer of the first redistribution substrate, and connects to the via of the first redistribution substrate. Thus, for purposes of examination, it is presumed that this is the feature being claimed as the wiring portion, as it is the only metallization that extends along the upper surface of an insulating layer of the first redistribution substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 12,272,651) in view of Jin et al. (US 2022/0077040).
Pertaining to claim 1, Shih shows, with reference to FIG. 2, a semiconductor package comprising:
a first redistribution substrate (101);
a chip structure (103) including a first semiconductor chip (103a) disposed on the first redistribution substrate;
a first interposer substrate (102a) including a through electrode (102b) extending through the first interposer substrate disposed on the first redistribution substrate, wherein the first interposer substrate is horizontally spaced apart from the chip structure;
a second semiconductor chip (104a) disposed on the first interposer substrate and electrically connected to the through electrode; and
a first molding layer (108) on the chip structure, the first interposer substrate, and the second semiconductor chip;
wherein a lower surface of the chip structure and a lower surface of the first interposer
substrate are in electrical contact with an upper surface of the first redistribution substrate.
Shih fails to show a connection substrate disposed on the first redistribution substrate and having an opening in which the chips reside, and a second redistribution substrate on the first molding layer and the connection substrate.
However, Jin teaches in FIG. 11 that, for a package similar to Shih, a connection substrate 300 is disposed on redistribution substrate 100 and has an opening 390 in which the chips reside. Jin further teaches another redistribution substrate 600 disposed on molding layer 400 and connection substrate 300.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Shih by including the connection substrate and the redistribution substrate taught by Jin, with the motivation that this allows for connection to an additional chip 720 (see FIG. 10A), thereby allowing for additional functionality within the package.
Pertaining to claim 2, Shih shows a second molding layer (107) on the second semiconductor chip, wherein a side surface of the second molding layer is vertically aligned with a side surface of the first interposer substrate.
Pertaining to claim 3, Jin teaches the connection substrate includes an insulating pattern (320) and conductive patterns (310) inside the insulating pattern.
Pertaining to claim 4, Shih shows the first redistribution substrate includes an insulating layer (101c) and wiring patterns (101d/e/f) inside the insulating layer, and wherein one of the wiring patterns exposed on the upper surface of the first redistribution substrate is electrically connected to a chip pad (103b) on the lower surface of the chip structure and a substrate pad (102d) on the lower surface of the first interposer substrate.
Pertaining to claim 7, Shih shows the first interposer substrate includes a silicon interposer (col. 14, lines 10-11).
Pertaining to claim 8, Jin teaches an upper package (22) mounted on the second redistribution substrate through a substrate connection terminal (650), wherein the upper package includes: a package substrate (710); a fourth semiconductor chip (720, see FIG. 10A) mounted on the package substrate; and a fourth molding layer (730) on an upper surface of the package substrate and surrounding the fourth semiconductor chip.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Jin and Wu et al. (US 11,139,274).
Pertaining to claim 17, Shih shows, with reference to FIG. 2, a semiconductor package comprising:
a first redistribution substrate (101) having external connection terminals (101k) disposed on a lower surface thereof;
a first semiconductor chip (103a) provided on the first redistribution substrate;
a chip structure (104) provided on the first redistribution substrate, horizontally spaced apart from the first semiconductor chip, and including an interposer substrate (102a/c) including a through electrode (102b), a second semiconductor chip (104a) on the interposer substrate, and a first molding layer (107) surrounding the second semiconductor chip on the interposer substrate; and
a second molding layer (108) covering the first semiconductor chip and the chip structure;
wherein a lower surface of the first semiconductor chip and a lower surface of the chip structure are in direct contact with an upper surface of the first redistribution substrate, and
wherein a side surface of the first molding layer is vertically aligned with a side surface
of the interposer substrate.
Shih fails to show a passive element disposed on the lower surface of the first redistribution substrate, between the external connection terminals, and spaced apart from the external connection terminals; a connection substrate disposed on the first redistribution substrate and having an opening in which the chips reside; a second redistribution substrate on the first molding layer and the connection substrate; a package substrate mounted on the second redistribution substrate through a substrate connection terminal; a third semiconductor chip mounted on the package substrate; and a third molding layer surrounding the third semiconductor chip on the package substrate.
However, Jin teaches in FIG. 11 that, for a package similar to Shih, a connection substrate 300 is disposed on redistribution substrate 100 and has an opening 390 in which the chips reside. Jin further teaches another redistribution substrate 600 disposed on molding layer 400 and connection substrate 300, a third semiconductor chip 720 mounted on the package substrate, and a third molding layer 730 on an upper surface of the package substrate and surrounding the third semiconductor chip.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Shih by including the connection substrate and the redistribution substrate taught by Jin, with the motivation that this allows for connection to an additional chip 720 (see FIG. 10A), thereby allowing for additional functionality within the package.
Meanwhile, Wu teaches in FIG. 1A that, for a similar package structure, a passive element 12b is disposed on the lower surface of redistribution substrate 10, between the external connection terminals 17, and spaced apart from the external connection terminals.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Shih to include the passive element taught by Wu, with the motivation that the inclusion of the passive component allows for added functionality within the package itself.
Pertaining to claim 19, Shih shows an upper surface of the first semiconductor chip is positioned at a higher vertical level than an upper surface of the chip structure (FIG. 2).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shih (hereinafter referred to as “Shih”) in view of Jin and Wu as applied to claim 17 above, and further in view of Shih (US 12,142,596, hereinafter referred to as ‘596).
Shin in view of Jin and Wu teaches the package of claim 17, wherein the second semiconductor chips include a logic chip or a memory chip (col. 9, lines 46-47).
Shin in view of Jin and Wu fails to teach the package of claim 17, wherein the second semiconductor chip is provided in plural, wherein the second semiconductor chips are horizontally spaced apart from each other.
However, ‘596 teaches in FIG. 6 that, for a similar device, semiconductor chips in stacks 130 and 140 are provided on a same interposer 110 and horizontally spaced apart.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Shih to include additional second chips, as taught by ‘596, with the motivation that this provides for further functionality within the package.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Jin and Wu as applied to claim 17 above, and further in view of Kwon (US 2022/0384322).
Shin in view of Jin and Wu fails to teaches the package of claim 17, but fails to teach the details of the first redistribution substrate as claimed.
However, Kwon teaches in FIG. 2C that, for a package similar to Shih, the first redistribution substrate 100 includes an insulating layer (upper 101) and a wiring pattern (130/135/bottom segment of 350) in the insulating layer, wherein the wiring pattern includes: a wiring portion (bottom segment of 350) extending onto an upper surface of the insulating layer; and a via portion (below bottom segment of 350) passing through the insulating layer and connected to the wiring portion, wherein a width of the via portion narrows toward the upper surface of the first redistribution substrate.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Shih to have the first redistribution substrate taught by Kwon, with the motivation that Kwon’s first redistribution substrate teaches the details of the first redistribution substrate that allow for electrical connection from the chips to an external connection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
Prosecution Insights