DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 27 November 2023. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 10, 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (U.S. Patent Application Publication 2021/0399099).
Referring to Claim 1, Chu teaches a method for forming a semiconductor device, the method comprising: forming a first field effect transistor comprising a first source or drain (S/D) region (one of 225D), a second S/D region (225S -> 226, 228, 260; par. 30, 31), and a backside contact (262, 264), the backside contact (262, 264) comprising a lower portion and a wrap-around portion wrapping around a lower portion of the second S/D region (260 of 225S); and forming a second field effect transistor comprising a frontside contact (par. 21; “front-side source/drain contact vias”; see also the structure 280 of Fig. 16) on a S/D region (another of 225D) and a backside sacrificial region (252) below the S/D region (another of 225D). The term “sacrificial” is an intended use label that does not inherently provide for particular materials or structures. "The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). (see MPEP § 2131). The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. The recitation of does not distinguish the present invention over the prior art who teaches the structure as claimed. It is noted that the device as shown in Fig. 16 is upside down in terms of referencing relative orientation or direction with respect to terms such as “above” or “below”.
Referring to Claim 10, Chu further teaches forming a backside sacrificial region (252) below the first S/D region (one of 225D) and below the second S/D region (225S) in the first field effect transistor (see Fig. 9).
Referring to Claim 11, Chu further teaches flipping the semiconductor device (between Fig. 6 and 7) and exposing the backside sacrificial region (252) in the first field effect transistor (see Fig. 9).
Referring to Claim 13, Chu teaches in Fig. 16 for example, (noted that the device is shown upside down in terms of referencing relative orientation or direction with respect to terms such as “above” or “below”) a semiconductor device comprising: a first field effect transistor comprising a first source or drain (S/D) region (one of 225D), a second S/D region (225S -> 226, 228, 260; par. 30, 31), and a backside contact (262, 264), the backside contact (262, 264) comprising a lower portion and a wrap-around portion wrapping around a lower portion (260) of the second S/D region (225S); and a second field effect transistor comprising a frontside contact (par. 21; “front-side source/drain contact vias”; see also the structure 280 of Fig. 16) on a S/D region (another of 225D) and a backside sacrificial region (252) below the S/D region (another of 225D).
Allowable Subject Matter
Claims 2-9, 12 and 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method of claim wherein the backside sacrificial region below the S/D region in the second field effect transistor is between opposite sidewalls of a shallow trench isolation (STI) liner in combination with all of the limitations of claims 1 and 2. Claims 3-9 include the limitations of claim 1.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method further comprising recessing the exposed sidewalls of the second S/D region in combination with all of the limitations of claims 10-12.
Regarding Claim 14, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the backside sacrificial region below the S/D region in the second field effect transistor is between opposite sidewalls of a shallow trench isolation (STI) liner in combination with all of the limitations of claims 13 and 14. Claims 15-20 include the limitations of claim 14.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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