DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “The device of claim 10”. Claim 12 is unclear because Claim 10 is a method claim. In addition, Claim 12 recites “the oxide plug” that is not introduced in Claim 10 or claim 1. Appropriate correction is required.
In addition, Claim 12 recites “wherein the bottom ends of pores of the second porous region accessible through the opening are plugged up by the oxide plug of the metal barrier.” Claim 12 is unclear because Claim 11 states “the bottom ends of pores of the second porous region are etched and reach the metal barrier”. Therefore, the bottom ends of pores of the second porous region accessible through the opening can not be “plugged up by the oxide plug”. Appropriate correction is required.
For purposes of compact prosecution, Claim 12 will be interpreted to instead recite “The device of claim 11, further comprising an etching mask above at least the first porous region having an opening above the second porous region, wherein the bottom ends of pores of the second porous region accessible through the opening are not plugged up by the oxide plug of the metal barrier.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- 2 and 4-15 are rejected under 35 U.S.C. 103 as being unpatentable over El Sabahy et al. (“El Sabahy”), EP 3929981 (cited in the IDS dated 11/27/2023, all citations below are in relation to the US counterpart US 2023/0125974) in view of Voiron et al. (“Voiron”), US 2022/0352024 (the US counterpart to EP 3848988 cited in the IDS dated 11/27/2023).
Regarding Claim 1, El Sabahy discloses a method for obtaining an integrated device (Figs. 4A-4B; ¶ 0068), the method comprising:
forming a metal barrier layer (106; Figs. 4A-4B; ¶ 0010 “layer 106 to serve as a barrier layer”, 0018, 0074) above a substrate (102, Figs. 4A-4B; ¶ 0008, 0074);
forming an anodizable metal layer (108; Figs. 4A-4B; ¶ 0011-0013, 0075) on the metal barrier layer (Figs. 4A-4B; ¶ 0074),
anodizing a first region and a second region of the anodizable metal layer (Figs. 4A-4B; ¶ 0075) to obtain respectively a first porous region (412b; Figs. 4A-4B; ¶ 0076) and a second porous region (412a; Figs. 4A-4B; ¶ 0076) both comprising a plurality of substantially straight pores (412; Figs. 4A-4B; ¶ 0017, 0075 “with reference to FIG. 2A to form therein the porous structure 112 having a plurality of pores 412”) that extend from a top surface of the porous region (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”), perpendicularly (¶ 0017 “extend perpendicularly or substantially perpendicularly toward the conductive layer 106”) to the top surface of the porous region (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”), towards the metal barrier layer (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”);
forming an etching mask (402; Figs. 4A-4B; ¶ 0076) above (¶ 0076 “mask layer 402 is formed over the porous structure 112.”) at least the first porous region having an opening above the second porous region (Figs. 4A-4B; ¶ 0076 “mask layer 402 leaves open the top ends of a select set of pores 412a falling within the area 414 and blocks the top ends of the remaining set of pores 412b”); and
etching the bottom ends of pores of the second porous region (Figs. 4A-4B; ¶ 0078 “the bottom ends of the select set of pores 412a (which fall within the area 414) to be etched away”) through the opening of the etching mask (Figs. 4A-4B; ¶ 0078-0079).
El Sabahy does not disclose to obtain pores that form a device region, and pores in the first porous region that form a dicing line, the integrated device being delimited at least by the dicing line.
Voiron discloses to obtain pores (138; Fig. 4F; ¶ 0051) that form a device region (Fig. 4H; ¶ 0061 “the successive layers of metal, insulator, and then metal follow the contours of the first porous structure 124 resulting in the MIM stack 132 being embedded inside the first set of pores 138”), and pores (140; Fig. 4F; ¶ 0054) in the first porous region (126; Fig. 4F; ¶ 0054) that form a dicing line (Figs. 4F, 4O; ¶ 0037 “dicing area 136 corresponds to a section of the wafer 102 on which no functional circuits are to be built and through which one or more dicing lanes are designed to pass”, ¶ 0070 “a dicing lane that passes through the dicing area 136”), the integrated device being delimited at least by the dicing line (¶ 0037 “dicing lanes are the lanes along which the wafer 102 is diced/cut, after the wafer 102 has been processed, to obtain multiple dies or blocks each containing a given functional integrated circuit”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to obtain pores that form a device region, and pores in the first porous region that form a dicing line, the integrated device being delimited at least by the dicing line, as taught by Voiron, because the integrated device “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) and the “resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070) thereby improving the reliability of the integrated device.
Regarding Claim 2, El Sabahy does not disclose further comprising dicing the structure to be diced through at least the dicing line to obtain a diced integrated device.
Voiron discloses further comprising dicing the structure to be diced through at least the dicing line to obtain a diced integrated device (¶ 0070 “silicon wafer 102 may then be diced along a dicing lane that passes through the dicing area 136. The resulting structure (i.e., the structure to the right of the dicing area 136 in FIG. 4P) is a semiconductor structure with AAO embedded circuitry (a capacitor in this case)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have further comprising dicing the structure to be diced through at least the dicing line to obtain a diced integrated device, as taught by Voiron, because the integrated device “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) and the “resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070) thereby improving the reliability of the integrated device.
Regarding Claim 4, El Sabahy discloses wherein the bottom ends of the pores are plugged up by an oxide plug (114; Figs. 4A-4B; ¶ 0081, 0075, 0078) of the metal barrier layer (¶ 0075 “oxide of the conductive layer 106”), and wherein etching the bottom ends of pores of the second porous region through the opening of the etching mask comprises removing the oxide plug of the pores accessible through the opening (Figs. 4A-4B; ¶ 0077-0078).
Regarding Claim 5, El Sabahy does not disclose further comprising forming an anodization mask having at least one anodization opening delimiting the first porous region and the second porous region.
Voiron discloses further comprising forming an anodization mask (114; Fig. 4F; ¶ 0045-0046, 0048) having at least one anodization opening (116, 120; Fig. 4E; ¶ 0045) delimiting the first porous region (126; Figs. 4E-4F; ¶ 0047-0048) and the second porous region (124; Figs. 4E-4F; ¶ 0047-0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have further comprising forming an anodization mask having at least one anodization opening delimiting the first porous region and the second porous region, as taught by Voiron, because “mask layer 114 ensures that porous structures are formed substantially only in the” desired “regions” (Voiron ¶ 0048) thereby improving the performance and reliability of the integrated device.
Regarding Claim 6, El Sabahy does not disclose wherein the anodization mask has a first opening delimiting the first porous region and a second opening, separate from the first opening, delimiting the second porous region.
Voiron discloses wherein the anodization mask (114; Figs. 4E-4F; ¶ 0045-0048) has a first opening (120; Fig. 4E; ¶ 0045) delimiting the first porous region (126; Figs. 4E-4F; ¶ 0047) and a second opening (116; Fig. 4E; ¶ 0045), separate from the first opening (Figs. 4E-4F; ¶ 0045-0048), delimiting the second porous region (124; Figs 4E-4F; ¶ 0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have wherein the anodization mask has a first opening delimiting the first porous region and a second opening, separate from the first opening, delimiting the second porous region, as taught by Voiron, because “mask layer 114 ensures that porous structures are formed substantially only in the” desired “regions” (Voiron ¶ 0048) thereby improving the performance and reliability of the integrated device.
Regarding Claim 7, El Sabahy does not disclose further comprising depositing a stacked structure including a bottom electrode layer, a dielectric layer, and a top electrode layer inside a group of pores of the device region so as to form a capacitor of the integrated device.
Voiron discloses further comprising depositing a stacked structure (132; Fig. 4H ¶ 0061 “a metal-insulator-metal (MIM) stack 132 is deposited”) including a bottom electrode layer, a dielectric layer, and a top electrode layer (¶ 0061 “successive layers of metal, insulator, and then metal”) inside a group of pores (138; ¶ 0061 “formed in the first set of pores 138 of the first porous structure 124” and “embedded inside the first set of pores 138 of the first porous structure 124”) of the device region so as to form a capacitor (¶ 0070 “a capacitor”) of the integrated device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have further comprising depositing a stacked structure including a bottom electrode layer, a dielectric layer, and a top electrode layer inside a group of pores of the device region so as to form a capacitor of the integrated device, as taught by Voiron, because “the successive layers of metal, insulator, and then metal follow the contours of the first porous structure 124 resulting in the MIM stack 132 being embedded inside the first set of pores 138” (Voiron ¶ 0061) thereby forming a more compact integrated device, and it “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) thereby improving the performance and reliability of the integrated device.
Regarding Claim 8, El Sabahy does not disclose wherein the first porous region surrounds the second porous region.
Voiron discloses wherein the first porous region surrounds the second porous region (¶ 0037 “the dicing lanes are the lanes along which the wafer 102 is diced/cut, after the wafer 102 has been processed, to obtain multiple dies or blocks each containing a given functional integrated circuit”, ¶ 0038-0039, 0070).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have wherein the first porous region surrounds the second porous region, as taught by Voiron, “to obtain multiple dies or blocks each containing a given functional integrated circuit” (Voiron ¶ 0037) where “the resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070), thereby improving the performance and reliability of the integrated device.
Regarding Claim 9, El Sabahy does not disclose further comprising forming a passivation layer above the etching mask having an opening at the level of the dicing line.
Voiron discloses further comprising forming a passivation layer (154; Fig. 4M; ¶ 0066) above the etching mask (128) having an opening at the level of the dicing line (Fig. 4O; ¶ 0068 “pores 140 are covered directly by the passivation layer 154, which is removed over the second set of pores 140”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have further comprising forming a passivation layer above the etching mask having an opening at the level of the dicing line, as taught by Voiron, in order to have an insulation layer that protects the integrated device during the dicing process (Voiron ¶ 0070) thereby improving the reliability of the integrated device.
Regarding Claim 10, El Sabahy does not disclose wherein a plurality of integrated devices is obtained, the integrated devices being delimited by dicing lines arranged in a grid.
Voiron discloses wherein a plurality of integrated devices is obtained (¶ 0037 “the dicing lanes are the lanes along which the wafer 102 is diced/cut, after the wafer 102 has been processed, to obtain multiple dies or blocks each containing a given functional integrated circuit”, ¶ 0070 “the silicon wafer 102 may then be diced along a dicing lane that passes through the dicing area 136”), the integrated devices being delimited by dicing lines arranged in a grid (¶ 0037 “dicing area 136 corresponds to a section of the wafer 102 on which no functional circuits are to be built and through which one or more dicing lanes are designed to pass”, ¶ 0038-0039, 0070, 0077).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have wherein a plurality of integrated devices is obtained, the integrated devices being delimited by dicing lines arranged in a grid, as taught by Voiron, because the integrated device “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) and “the resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070) thereby improving the performance and reliability of the integrated device.
Regarding Claim 11, El Sabahy discloses an integrated device (400B; Figs. 4A-4B; ¶ 0073-0078) comprising:
a substrate (102; Figs. 4A-4B; ¶ 0008, 0074);
a metal barrier layer (106; Figs. 4A-4B; ¶ 0010 “layer 106 to serve as a barrier layer”, 0018, 0074) above the substrate (Figs. 4A-4B; ¶ 0008, 0074); and
a layer (108; Figs. 4A-4B; ¶ 0011-0013, 0075) including a first porous region of anodized metal (412b; Figs. 4A-4B; ¶ 0075 “layer 108 has been anodized”, 0076) and a second porous region (412a; Figs. 4A-4B; ¶ 0076) both comprising a plurality of substantially straight pores (412; Figs. 4A-4B; ¶ 0017, 0075 “with reference to FIG. 2A to form therein the porous structure 112 having a plurality of pores 412”) that extend from a top surface of the porous region (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”), perpendicularly (¶ 0017 “extend perpendicularly or substantially perpendicularly toward the conductive layer 106”) to the top surface of the porous region (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”), towards the metal barrier layer (Figs. 4A-4B; ¶ 0017 “pores that extend from a top surface of the porous structure 112 toward the conductive layer 106”),
wherein the bottom ends of pores of the first porous region are plugged up by an oxide plug (114; Fig. 4B; ¶ 0078 “the bottom ends of the set of pores 412b remain filled by oxide plugs 114”) of the metal barrier (¶ 0075 “oxide of the conductive layer 106”, ¶ 0018 “The formed oxide of the conductive layer 106 creates oxide plugs 114”).
El Sabahy does not disclose
the bottom ends of pores of the second porous region are etched and reach the metal barrier so as to form a device region, and
wherein pores in the first porous region form a dicing line.
Voiron discloses
the bottom ends of pores of the second porous region are etched (this limitation is not given patentable weight because it is a method step in a structure claim) and reach the metal barrier (Fig. 4F; ¶ 0051 “pores 138 that extend from a top surface of the first porous structure 124 to barrier layer 108”, “any residual material at the bottoms of the first set of pores 138 may be etched to fully open the first set of pores 138 onto the barrier layer 108”) so as to form a device region (Fig. 4H; ¶ 0061 “successive layers of metal, insulator, and then metal follow the contours of the first porous structure 124 resulting in the MIM stack 132 being embedded inside the first set of pores 138”), and
wherein pores (140; Fig. 4F; ¶ 0054) in the first porous region (126; Fig. 4F; ¶ 0054) form a dicing line (Figs. 4F, 4O; ¶ 0037 “dicing area 136 corresponds to a section of the wafer 102 on which no functional circuits are to be built and through which one or more dicing lanes are designed to pass”, ¶ 0070 “a dicing lane that passes through the dicing area 136”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have the bottom ends of pores of the second porous region are etched and reach the metal barrier so as to form a device region, and wherein pores in the first porous region form a dicing line, as taught by Voiron, because the integrated device “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) and the “resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070) thereby improving the reliability of the integrated device.
Regarding Claim 12, El Sabahy discloses further comprising an etching mask (402; Fig. 4B; ¶ 0076) above at least the first porous region (Fig. 4B; ¶ 0076 “the mask layer 402…blocks the top ends of the remaining set of pores 412b falling outside the area 414”) having an opening above the second porous region (Fig. 4B; ¶ 0076 “the mask layer 402 leaves open the top ends of a select set of pores 412a falling within the area 414”), wherein the bottom ends of pores of the second porous region accessible through the opening are not plugged up by the oxide plug of the metal barrier (Fig. 4B; ¶ 0076).
Regarding Claim 13, El Sabahy does not disclose wherein the first porous region surrounds the second porous region.
Voiron discloses wherein the first porous region surrounds the second porous region (¶ 0037 “the dicing lanes are the lanes along which the wafer 102 is diced/cut, after the wafer 102 has been processed, to obtain multiple dies or blocks each containing a given functional integrated circuit”, ¶ 0038-0039, 0070).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have wherein the first porous region surrounds the second porous region, as taught by Voiron, “to obtain multiple dies or blocks each containing a given functional integrated circuit” (Voiron ¶ 0037) where “the resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070), thereby improving the performance and reliability of the integrated device.
Regarding Claim 14, El Sabahy does not disclose further comprising a stacked structure including a bottom electrode layer, a dielectric layer, and a top electrode layer inside a group of pores of the device region so as to form a capacitor of the integrated device.
Voiron discloses further comprising a stacked structure (132; Fig. 4H ¶ 0061 “a metal-insulator-metal (MIM) stack 132 is deposited”) including a bottom electrode layer, a dielectric layer, and a top electrode layer (¶ 0061 “successive layers of metal, insulator, and then metal”) inside a group of pores (138; ¶ 0061 “formed in the first set of pores 138 of the first porous structure 124” and “embedded inside the first set of pores 138 of the first porous structure 124”) of the device region so as to form a capacitor (¶ 0070 “a capacitor”) of the integrated device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have further comprising a stacked structure including a bottom electrode layer, a dielectric layer, and a top electrode layer inside a group of pores of the device region so as to form a capacitor of the integrated device, as taught by Voiron, because “the successive layers of metal, insulator, and then metal follow the contours of the first porous structure 124 resulting in the MIM stack 132 being embedded inside the first set of pores 138” (Voiron ¶ 0061) thereby forming a more compact integrated device, and it “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) thereby improving the performance and reliability of the integrated device.
Regarding Claim 15, El Sabahy does not disclose wherein the integrated device is diced.
Voiron discloses wherein the integrated device is diced (¶ 0037 “the dicing lanes are the lanes along which the wafer 102 is diced/cut, after the wafer 102 has been processed, to obtain multiple dies or blocks each containing a given functional integrated circuit”, ¶ 0070 “silicon wafer 102 may then be diced along a dicing lane that passes through the dicing area 136”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy to have wherein the integrated device is diced, as taught by Voiron, because the integrated device “has an improved mechanical profile, including reduced delamination, chipping, and cracks in the supporting substrate” (Voiron ¶ 0070) and the “resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the influent of humidity and the risk of leakage, particularly due to the wafer bumping process” (Voiron ¶ 0070) thereby improving the reliability of the integrated device.
Moreover, the Claim 15 limitation of “is diced” comprises a product by process limitation, and is not given patentable weight in a claim drawn to structure. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over El Sabahy et al. (“El Sabahy”), US 2023/0125974 (the US counterpart to EP 3929981 cited in the IDS dated 11/27/2023) and Voiron et al. (“Voiron”), US 2022/0352024 (the US counterpart to EP 3848988 cited in the IDS dated 11/27/2023), as applied to Claim 1 supra, in view of Fachmann et al. (“Fachmann”), US 2022/0352048.
El Sabahy as modified by Voiron does not disclose wherein the dicing comprises performing a mechanical blade dicing.
Fachmann discloses wherein the dicing comprises performing a mechanical blade dicing (¶ 0016 “dicing…mechanically, e.g. by blade dicing”, ¶ 0080).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for El Sabahy as modified by Voiron to have wherein the dicing comprises performing a mechanical blade dicing, as taught by Fachmann, because mechanical blade dicing is a well known and widely used dicing process, thereby providing process predictability and improving the reliability of the integrated device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Voiron et al., US 2021/0066449, discloses a structure and a method of making the structure (such as a capacitor) that has a barrier layer, a porous region, and oxide plugs. Oukassi et al., US 2021/0074477, discloses a 3D capacitive component formed in an anodizable metal layer that is on a metal barrier layer (that is above a substrate). Voiron et al., US 2021/0332492, discloses a structure and a method of forming the structure, such as a 3D capacitor, formed in a metal layer that has been anodized to form porous regions.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818