DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 and 13-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Attarwala, US Patent Application Publication 2004/0195701
Regarding claim 10, Attarwala teaches a semiconductor device comprising:
a package substrate 24, 124 having a first major side and a second major side;
a cavity 25 formed in the package substrate, the cavity having an opening at the first major side;
a plurality of metal redistribution traces 144, 132, 136 formed at the first major side, the plurality of redistribution traces substantially surrounding the cavity;
a semiconductor die 30 mounted in the cavity;
a wire bond 34 having a first end affixed at a bond pad of the semiconductor die and a second end affixed at a wiring pad region of a redistribution trace of the plurality of redistribution traces;
an encapsulant 36, 136 encapsulating the semiconductor die and the first major side of the package substrate;
a base region (where ball contact 38 is located) of the redistribution trace exposed through the encapsulant; and
an under-bump metallization (UBM) structure 38 formed on the exposed base region (figures 6-10).
Regarding claims 13-15, Attarwala teaches a metal layer 122 formed at the second major side of the package substrate, wherein the cavity formed in the package substrate exposes a portion of the metal layer formed at the second major side of the package substrate, wherein the semiconductor die mounted in the cavity includes a backside of the semiconductor die affixed to the exposed portion of the metal layer by way of a die attach film 32 (DAF) (figure 7).
Regarding claim 16, Attarwala teaches a method comprising:
forming a plurality of redistribution traces 144, 132, 136 at a first major side of a package substrate 24,124;
forming a cavity 25 in the package substrate, the plurality of redistribution traces substantially surrounding an opening of the cavity at the first major side (Note: figure 2 shows that ball contact 38 that substantially surrounds the first cavity, thereby also teaching that the redistribution traces 142,132,136 surrounds the first cavity);
mounting a semiconductor die 30 in the cavity;
forming a wire bond 34 between a bond pad of the semiconductor die and a wiring pad region of a redistribution trace of the plurality of redistribution traces;
encapsulating with an encapsulant 36,136 the semiconductor die and the first major side of the package substrate; and
exposing a base region of the redistribution trace (to form umb 38. Figures 6-10).
Regarding claims 17-18, Attarwala teaches forming the cavity in the package substrate includes exposing a portion of a second metal layer 122 formed at a second major side of the package substrate, wherein mounting the semiconductor die in the cavity includes affixing a backside of the semiconductor die on the exposed second metal layer portion by way of a die attach film (DAF) 32 (figure 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala, US Patent Application Publication 2004/0195701 in view of Ohsawa et al, US Patent 5,786,239.
Regarding claim 1, Attarwala teaches a method comprising:
patterning a first metal layer at a first major side of a package substrate to form a plurality of redistribution traces 144, 132, 136;
forming a first cavity 25 (figure 6) in the package substrate 124, the plurality of redistribution traces substantially surrounding the first cavity (Note: figure 2 shows that ball contact 38 that substantially surrounds the first cavity, thereby also teaching that the redistribution traces 142,132,136 surrounds the first cavity);
mounting a semiconductor die 30 in the first cavity;
forming a wire bond 34 between a bond pad of the semiconductor die and a wiring pad region of a redistribution trace of the plurality of redistribution traces;
encapsulating with an encapsulant the semiconductor die (with 136) and the first major side of the package substrate (with 36);
exposing a base region of the redistribution trace (to form 38 in the base region); and
forming an under-bump metallization (UBM) structure 38 on the exposed base region (figures 6-10).
Attarwala fails to teach forming the UBM is by selectively plating
Ohsawa teaches forming the UBM is by selectively plating (column 5, lines 45-49) as a generally-known means of depositing a UBM layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ohsawa with that of Attarwala because selective plating is a generally-known means of depositing a UBM layer.
Regarding claim 3, Ohsawa teaches selectively plating the UBM structure includes filling the second cavity with a copper or copper alloy material (column 6, lines 36-39)
Regarding claim 4, Attarwala teaches affixing a conductive package connector on the UBM structure (by teaching the ball contact, which has ubm structure as 38 disposed in layer 136 and upper portion 38 above the surface of 38).
Regarding claim 5, Attarwala teaches forming the first cavity includes exposing a portion of a second metal layer 22 at a second major side of the package substrate (figure 6 AND [0083]).
Regarding claim 7, Attarwala teaches mounting the semiconductor die in the first cavity includes affixing a backside of the semiconductor die to the exposed second metal layer portion by way of a die attach film (DAF) 32 (figure 7).
Regarding claim 8, Ohsawa and Attarwala the first metal layer at the first major side (Ohsawa, item 6, column 5, lines 45-46) and the second metal layer at the second major side (Attarwala, [111]) are formed from a copper or copper alloy material.
Regarding claim 9, Attarwala teaches the package substrate is characterized as a metal clad FR4 substrate (claim 5, with metal layers 138).
Claim(s) 11, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala as applied to claims 10 above, and further in view of Ohsawa et al, US Patent 5,786,239.
Regarding claim 11, Attarwala fails to teach the UBM structure is characterized as a structure formed by way of plating a copper or copper alloy material.
Ohsawa teaches the UBM structure is characterized as a structure formed by way of plating a copper or copper alloy material (column 6, lines 36-39) because copper is a generally-known material that is conventionally used in semiconductor devices as a redistribution trace.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ohsawa with that of Attarwala because copper is a generally-known material that is conventionally used in semiconductor devices due to its excellent electrical conduction capability.
Regarding claim 19, Attarwala teaches forming an under-bump metallization (UBM) structure 38 on the exposed base region of the redistribution trace (figure 7)
Attarwala fails to teach forming the UBM is by selectively plating
Ohsawa teaches forming the UBM is by selectively plating (column 5, lines 45-49) as a generally-known means of depositing a UBM layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ohsawa with that of Attarwala because selective plating is a generally-known means of depositing a UBM layer.
Regarding claim 20, Attarwala teaches affixing a conductive package connector on the UBM structure (by teaching the ball contact, which has ubm structure as 38 disposed in layer 136 and upper portion 38 above the surface of 38).
Claim(s) 2, 6, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala and Ohsawa as applied to claims 1, 10, and above, and further in view of Eichelberger, US Patent 5,111,278
Regarding claim 2, Attarwala teaches exposing the base region of the redistribution trace includes forming a second cavity in the encapsulant by way of a removal, the base region of the redistribution trace exposed at the bottom of the second cavity (in which the second cavity is filled with ball contact is located in 136)
Attarwala and Ohsawa fail to teach the removal is by way of laser ablation.
Eichelberger teaches the removal is by way of laser ablation (column 16, lines 62-66) as a known means of forming holes in a dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eichelberger with that of Attarwala and Ohsawa because laser ablation is a known means of forming holes in a dielectric layer.
Regarding claim 6, Attarwala teaches forming the first cavity in the package substrate includes a removal to form the first cavity and expose the portion of the second metal layer (figure 6).
Attarwala and Ohsawa fail to teach the removal is by way of laser ablation.
Eichelberger teaches the removal is by way of laser ablation (column 16, lines 62-66) as a known means of forming holes in a dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eichelberger with that of Attarwala and Ohsawa because laser ablation is a known means of forming holes in a dielectric layer.
Regarding claim 12, Attarwala fails to teach the cavity in the package substrate is formed by way of laser ablation.
Eichelberger teaches the cavity in the package substrate is formed by way of laser ablation (column 16, lines 62-66) as a known means of forming holes in a dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eichelberger with that of Attarwala and Ohsawa because laser ablation is a known means of forming holes in a dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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