DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamaji (PG Pub. No. US 2015/0236013 A1).
Regarding claim 1, Yamaji teaches a semiconductor device (fig. 13: 200a) comprising:
a substrate body (¶ 0032: 1) of a first conductivity-type (p-type);
a first well region (¶ 0022: 3) of a second conductivity-type (n-type) provided in the substrate body (fig. 14A among others: 3 provided in 1) and provided with a high-side circuit (¶ 0087: 3 provided with HVJT 193);
a first voltage blocking region (¶¶ 0023, 0027: region 4 of voltage blocking element 46) of the second conductivity-type (n-type) provided around the first well region (fig. 13: 4 provided around 3) and having a lower impurity concentration than the first well region (¶ 0077: 4 has lower impurity concentration than 3);
a contact region (¶ 0094: 62) of the second conductivity-type (n-type) provided at an upper part of the first well region or the first voltage blocking region (fig. 14B: 62 provided at upper part of 4) and having a higher impurity concentration than the first well region (¶ 0029: 62 is a high concentration region);
a second voltage blocking region (¶¶ 0027. 0029: region 61 of voltage blocking element 46) of the first conductivity-type (p-type) provided on an outer circumferential side of the first voltage blocking region (fig. 13: 61 formed an outer circumferential side of 4) so as to be in contact with the first voltage blocking region (figs. 13-14A: 61 contacts 4);
a first isolation region (¶ 0086: 63) of the first conductivity-type (p-type) provided to electrically isolate, from the first well region, an opposed part of the first voltage blocking region (fig. 14: 63 isolates 3 from a portion of 4) opposed to a low-side circuit provided on an outer circumferential side of the second voltage blocking region (fig. 13: at least a portion of 63 arranged on side of 4 opposite to low side circuit region); and
a level shifter (¶ 0107: 41) provided to execute a signal transmission between the low-side circuit and the high-side circuit (¶ 0107).
Regarding claim 2, Yamaji teaches the semiconductor device of claim 1, further comprising a resistor (¶ 0017: 71 or 72) arranged to connect the opposed part and the contact region to each other (figs. 10A-10B, 13: 71/72 of HVIC at least indirectly arranged between opposed portion of 4 and 62).
Regarding claim 3, Yamaji teaches the semiconductor device of claim 1, further comprising:
a second well region (¶ 0029: 31) of the first conductivity-type (p-type) provided at the upper part of the first well region (fig. 11: 31 provided at upper part of 3); and
a diode connected between the second well region and a carrier-reception region of the level shifter (¶ 0045: region 38 is n-type, forming a diode with p-type region 31).
Regarding claim 6, Yamaji teaches the semiconductor device of claim 1, wherein the level shifter is provided on the outer circumferential side of the second voltage blocking region (fig. 13).
Regarding claim 7, Yamaji teaches the semiconductor device of claim 1, wherein:
the first voltage blocking region has an outline with a rectangular shape in a planar pattern (fig. 13: 4 substantially rectangular w/ rounded corners); and
the opposed part includes two corners toward the low-side circuit among four corners of the rectangular shape (fig. 13: low side circuit includes two lower rounded corners of 4)).
Regarding claim 8, Yamaji teaches the semiconductor device of claim 1, further comprising a level-shift resistor (¶ 0013: 72) connected between a carrier-reception region of the level shifter and the contact region (figs. 10B, 13).
Regarding claim 9, Yamaji teaches the semiconductor device of claim 1, wherein both ends of the isolation region are in contact with the second voltage blocking region (fig. 13: both ends of 63 in contact with 61).
Regarding claim 10, Yamaji teaches the semiconductor device of claim 1, wherein the opposed part includes an entire part of the first voltage blocking region opposed to the low-side circuit (figs. 12-13: in at least one embodiment, opposed part of 4 includes an entire part of 4 opposed to the low-side circuit).
Regarding claim 11, Yamaji teaches the semiconductor device of claim 1, wherein the opposed part includes at least a middle of a part of the first voltage blocking region opposed to the low-side circuit (figs. 13, 14A: middle of 4 opposes low side circuit).
Regarding claim 12, Yamaji teaches the semiconductor device of claim 1, wherein the level shifter is provided integrally with a part of each of the first voltage blocking region and the second voltage blocking region (fig. 13: level shifter of 41 integrated with 4 and 61).
Regarding claim 13, Yamaji teaches the semiconductor device of claim 12, wherein:
the first voltage blocking region has an outline with a rectangular shape in a planar pattern (fig. 13: 4 includes substantially rectangular shape with rounded corners); and
the level shifter is provided on one of four sides of the rectangular shape not opposed to the low-side circuit (fig. 13: level shifter of 41 arranged on side of 4 not opposed to low side circuit).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaji as applied to claim 2 above, and further in view of Watase et al. (PG Pub. No. US 2007/0132096 A1).
Regarding claims 4-5, Yamaji teaches the semiconductor device of claim 2, comprising a resistor (71 and/or 72).
Yamaji does not teach wherein the resistor is a polysilicon resistor (as recited in claim 4), or
wherein the resistor is a diffusion resistor (as recited in claim 5).
Watase teaches circuits comprising diffusion and/or polysilicon resistors (¶ 0006, fig. 7: 112).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the resistor of Yamaji as a diffusion or polysilicon resistor, as a means to form the resistor in a manner compatible with impurity diffusion regions and/or polysilicon gate structures, optimizing manufacturing efficiency.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the resistor of Watase could have been combined the circuit of Yamaji by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art.
Allowable Subject Matter
Claims 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or clearly suggest a drift region of a level shifter, as required by claims 14 and 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/Examiner, Art Unit 2818