DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested: “WAFER DICING METHOD FORMING INTERNAL CRACKS BY LASER BEAM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME.”
If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed.
Claim Objections
Claims 16-20 are objected to because of the following informalities:
In claim 16, line 5, substitute “the” with --a-- before “wafer.”
Claims 17-20 depend from claim 16, so they are objected for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7, 8, 10-13, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saeki et al. (US Pub. 2019/0304838; hereinafter “Saeki”) in view Nakamura (US Pub. 2011/0081768).
Regarding Claim 1, Saeki discloses a wafer dicing method, comprising: preparing a wafer 101 (page 3, paragraph 41) having a plurality of device formation areas 120 and a scribe lane area 110 between the plurality of device formation areas 120 (page 3, paragraph 37; see fig. 2B); forming a plurality of semiconductor devices (semiconductor circuitry; page 3, paragraph 38) in the respective plurality of device formation areas 120 of the wafer 101 (see fig. 3B); forming, in the scribe lane area 110, a plurality of first grooves 111 partially passing through at least a portion of the wafer 101 in a vertical direction (page 3, paragraphs 44-46; see fig. 4B); forming a plurality of second grooves 111 by planarizing lower surfaces of the plurality of first grooves 111 (page 3, paragraph 46; see fig. 4C); and separating the plurality of semiconductor devices (semiconductor circuitry) from each other (page 6, paragraph 78; see figs. 8A and 8B).
Saeki fails to disclose explicitly wherein forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves; and separating the plurality of semiconductor devices from each other along the one or more internal cracks.
However, Nakamura discloses forming a modified area 6 by irradiating a laser beam 41 along a dividing line L between functional elements D on a front surface W1 of a wafer W (page 2, paragraph 28; see fig. 28). Further, Nakamura discloses the modified area 6 is a cracking area (page 2, paragraph 34), and that the wafer W is divided along all predetermined dividing lines L from the modified areas 6 (page 2, paragraph 35). Accordingly, the cracking area forms an internal crack from which the wafer W is divided.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use modified regions or internal cracks to divide a substrate, as taught by Nakamura, in order to reduce plasma-induced damage, minimize kerf loss, simplify processing, and improve die yield and reliability, as compared to the plasma dicing method disclosed in Saeki.
Regarding Claim 2, Saeki fails to disclose explicitly wherein the planarizing of the lower surfaces of the plurality of first grooves comprises configuring the lower surface of each of the plurality of first grooves to have a roughness of less than or equal to about 0.08 micrometers.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because determining optimum process conditions would have involved no more than routine experimentation using a limited number of result-effective variables. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Furthermore, achieving a surface roughness of less than or equal to 0.08 micrometers reduces surface defects and stress concentrations, thereby improving mechanical strength, device reliability, and compatibility with subsequent fabrication processes.
Regarding Claim 3, Saeki discloses wherein the forming of the plurality of first grooves 111 in the scribe lane area 110 comprises performing a laser etching method or a plasma etching method (page 3, paragraphs 46 and 48; see fig. 4B).
Regarding Claim 4, Saeki discloses wherein the planarizing of the lower surfaces of the plurality of first grooves 111 comprises performing a laser etching method or a chemical mechanical polish (CMP) method (page 3, paragraph 46; pag4, paragraph 53; see fig. 4C).
Regarding Claim 7, Saeki discloses wherein a range of a width (a width of dicing regions 110) of each of the plurality of second grooves 111 in a horizontal direction (see figs. 4A-4C) is from about 10 micrometers to about 100 micrometers (page 3, paragraph 40).
Regarding Claim 8, Saeki discloses a method of manufacturing a semiconductor device, the method comprising: preparing a wafer 101 (page 3, paragraph 41) having a plurality of device formation areas 120 and a scribe lane area 110 between the plurality of device formation areas 120 (page 3, paragraph 37; see fig. 2B); forming a plurality of semiconductor devices (semiconductor circuitry; page 3, paragraph 38) in the plurality of device formation areas 120 of the wafer 101 (see fig. 3B); forming a plurality of insulating layers 102a and a wiring layer 102b on the wafer 101 (page 9, paragraph 123; see fig. 3B); forming, in the scribe lane area 110, a plurality of first grooves 111 partially passing through at least a portion of the wafer 101 in a vertical direction (page 3, paragraphs 44-46; see fig. 4B); forming a plurality of second grooves 111 by planarizing lower surfaces of the plurality of first grooves 111 (page 3, paragraph 46; see fig. 4C); separating the plurality of semiconductor devices (semiconductor circuitry) from each other (page 6, paragraph 78; see figs. 8A and 8B); and packaging each of the plurality of semiconductor devices responsive to the separating (the substrate 10 is diced or separate into a plurality of element of chips 30 each including the element regions 110; page 6, paragraph 78; each element chip 30 can then be processed into a packaged semiconductor), wherein the plurality of first grooves 111 pass through at least one of the plurality of insulating layers 102a and the wiring layer 102b in the vertical direction (see fig. 4B).
Saeki fails to disclose explicitly wherein forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves; separating the plurality of semiconductor devices from each other along the one or more internal cracks.
However, Nakamura discloses forming a modified area 6 by irradiating a laser beam 41 along a dividing line L between functional elements D on a front surface W1 of a wafer W (page 2, paragraph 28; see fig. 28). Further, Nakamura discloses the modified area 6 is a cracking area (page 2, paragraph 34), and that the wafer W is divided along all predetermined dividing lines L from the modified areas 6 (page 2, paragraph 35). Accordingly, the cracking area forms an internal crack from which the wafer W is divided.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use modified regions or internal cracks to divide a substrate, as taught by Nakamura, in order to reduce plasma-induced damage, minimize kerf loss, simplify processing, and improve die yield and reliability, as compared to the plasma dicing method disclosed in Saeki.
Regarding Claim 10, Saeki fails to disclose explicitly wherein the plurality of second grooves and the one or more internal cracks respectively overlap each other in the vertical direction.
However, Nakamura discloses forming the modified area 6 within the dividing line L by bringing a laser beam irradiation section 4 at a position above the predetermined diving line L (page 2, paragraph 28; see fig. 5). Saeki discloses the plurality of second grooves 111 formed within the dicing region 110 (see fig. 4C). Because Nakamura’s modified area 6 is formed beneath the dividing line L, a modified area is correspondingly formed beneath the plurality of second grooves 111, overlapping in the vertical direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form modified regions or internal cracks that vertically overlap a plurality of grooves within the dicing regions, in order to separate the substrate into a plurality of individual chips only along the dicing regions.
Regarding Claim 11, Saeki fails to disclose explicitly wherein the lower surfaces of the plurality of second grooves and the one or more internal cracks are spaced apart from each other in the vertical direction.
However, Nakamura discloses forming the modified area 6 inside of the wafer W (page 2, paragraph 28) and spaced apart form a surface of the wafer W in the vertical direction (see fig. 5). Saeki discloses the plurality of second grooves 111 formed within the dicing region 110 (see fig. 4C). Because Nakamura’s modified area 6 is formed beneath the dividing line L and spaced apart form a surface of the wafer W, a modified area is correspondingly formed beneath the plurality of second grooves 111 and spaced apart from the lower surfaces of the plurality of second grooves in the vertical direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form modified regions or internal cracks that are vertically spaced apart from the lower surfaces of a plurality of grooves within the dicing regions, in order to promote controlled fracture along the dicing regions while preventing damage to adjacent element regions.
Regarding Claim 12, Saeki fails to disclose explicitly wherein the separating of the plurality of semiconductor devices comprises: attaching a dicing tape onto a back surface of the wafer; and stretching the dicing tape in a horizontal direction.
However, Nakamura discloses attaching a workpiece 2 to an adhesive surface of an expansion tape T (page 2, paragraph 19; see fig. 1), and stretching the expansion tape T in a horizontal direction (A-direction in fig. 6) separating into individual devices 7 (page 2, paragraph 35).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a dicing tape, as taught by Nakamura, in order to enable clean and controlled chip separation by applying uniform tensile stress reducing chipping, cracking, and damage to the individual chips.
Regarding Claim 13, Saeki discloses wherein strengths of the plurality of insulating layers 102a (silicon dioxide; page 3, paragraph 42) are less than a strength of the wafer 101 (silicon; page 3, paragraph 41). Multiple insulating layers (for example silicon oxide or silicon nitride layers) are mechanically weaker than the wafer as a whole (typically a silicon substrate).
Regarding Claim 16, Saeki discloses a method of manufacturing a semiconductor device, the method comprising: preparing a plurality of device formation areas 120 and a scribe lane area 110 between the plurality of device formation areas 120 (page 3, paragraph 37; see fig. 2B); forming a plurality of semiconductor devices (semiconductor circuitry) in the plurality of device formation areas 120 (page 3, paragraph 38) of a wafer 101 (page 3, paragraph 41); forming a plurality of insulating layers 102a and a wiring layer 102b on the wafer 101 (page 9, paragraph 123; see fig. 3B); forming, in the scribe lane area 110, a plurality of first grooves 111 partially passing through at least a portion of the wafer 101 in a vertical direction (page 3, paragraphs 44-46; see fig. 4B); forming a plurality of second grooves 111 by planarizing lower surfaces of the plurality of first grooves 111 (page 3, paragraph 46; see fig. 4C); separating the plurality of semiconductor devices (semiconductor circuitry) from each other (page 6, paragraph 78; see figs. 8A and 8B); and packaging each of the plurality of semiconductor devices responsive to the separating (the substrate 10 is diced or separate into a plurality of element of chips 30 each including the element regions 110; page 6, paragraph 78; each element chip 30 can then be processed into a packaged semiconductor), wherein the forming of the plurality of first grooves 111 in the scribe lane area 110 comprises performing at least one of a laser etching method using a first laser device, and a plasma etching method (an ablation laser beam La laser device; page 3, paragraphs 46 and 48), the planarizing of the lower surfaces of the plurality of first grooves 111 comprises performing at least one of a laser etching method using a second laser device, and a chemical mechanical polish (CMP) method (a melting laser beam Lm laser device; page 3, paragraph 46; page 4, paragraph 53), and the plurality of first grooves 111 pass through at least one of the plurality of insulating layers 102a and the wiring layer 102b in the vertical direction (see fig. 4B).
Saeki fails to disclose explicitly wherein forming one or more internal cracks in the wafer by irradiating the scribe lane area with a laser beam along lower surfaces of the plurality of second grooves; separating the plurality of semiconductor devices from each other along the one or more internal cracks; and the forming of the one or more internal cracks comprises performing a laser etching method using a third laser device.
However, Nakamura discloses forming a modified area 6 by irradiating a laser beam 41 using a laser device 4 along a dividing line L between functional elements D on a front surface W1 of a wafer W (page 2, paragraph 28; see fig. 28). Further, Nakamura discloses the modified area 6 is a cracking area (page 2, paragraph 34), and that the wafer W is divided along all predetermined dividing lines L from the modified areas 6 (page 2, paragraph 35). Accordingly, the cracking area forms an internal crack from which the wafer W is divided.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use modified regions or internal cracks to divide a substrate, as taught by Nakamura, in order to reduce plasma-induced damage, minimize kerf loss, simplify processing, and improve die yield and reliability, as compared to the plasma dicing method disclosed in Saeki.
Regarding Claim 17, Saeki discloses wherein the forming of the plurality of first and second grooves 111 comprises using the first and second laser devices, respectively (an ablation laser beam La laser device and a melting laser beam Lm laser device; page 3, paragraph 46), to etch at least a portion of each of the plurality of insulating layers 102a or the wafer 101 (see figs. 4A-4C).
Saeki fails to disclose explicitly wherein the forming of the one or more internal cracks comprises using the third laser device to reform at least a portion of the wafer by irradiating a laser beam to an area inside of the wafer.
However, Nakamura discloses forming a modified area 6 inside of a wafer W by irradiating a laser beam 41 using a laser device 4 along a dividing line L between functional elements D (page 2, paragraph 28; see fig. 28).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use modified regions or internal cracks to divide a substrate, as taught by Nakamura, in order to reduce plasma-induced damage, minimize kerf loss, simplify processing, and improve die yield and reliability, as compared to the plasma dicing method disclosed in Saeki.
Regarding Claim 18, Saeki in view of Nakamura discloses wherein an irradiation range of a laser beam generated by the second laser device (the melting laser beam Lm laser device) is wider than an irradiation range of the laser beam generated by the third laser device (the modified-area-forming laser device) (the melting laser beam Lm is irradiated over a width corresponding to the hole width 110 of the plurality of first grooves 111 (see figs. 4B and 4C), whereas the modified-area-forming laser beam 41 is irradiated with a width smaller than that of the diving line L so that material modification is confined within the dividing line L (see fig. 5)).
Regarding Claim 20, Saeki discloses wherein a range of a horizontal width (a width of dicing regions 110) of each of the plurality of second grooves 111 (see figs. 4A-4C) from about 10 micrometers to about 100 micrometers (page 3, paragraph 40).
Saeki fails to disclose explicitly wherein forming the plurality of second grooves comprises forming the lower surface of each of the plurality of second grooves to have a surface roughness of less than or equal to about 0.08 micrometers
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because determining optimum process conditions would have involved no more than routine experimentation using a limited number of result-effective variables. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Furthermore, achieving a surface roughness of less than or equal to 0.08 micrometers reduces surface defects and stress concentrations, thereby improving mechanical strength, device reliability, and compatibility with subsequent fabrication processes.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Saeki in view Nakamura, and further in view of Hashimoto (US Pub. 2022/0288722).
Regarding Claim 15, Saeki in view of Nakamura fails to disclose explicitly wherein further comprising grinding a back surface of the wafer after the forming of the one or more internal cracks in the wafer.
However, Hashimoto discloses a wafer 11 is thinned by being ground on a back surface 11b of the wafer 11 (page 9, paragraphs 102 and 108) after forming of modified regions 37 (page 9, paragraph 99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to grind a back surface of a wafer after forming internal cracks, in order to reduce the wafer thickness and propagate the internal cracks toward the back surface, thereby enabling controlled separation of the wafer into individual chips while minimizing damage to device regions.
Allowable Subject Matter
Claims 5, 6, 9, 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites a first laser beam for planarizing the lower surfaces of the plurality of first grooves has a different wavelength and irradiation area relative to a second laser beam for forming the one or more internal cracks.
Claim 6 recites the planarizing of the lower surfaces of the plurality of first grooves comprises removing at least a portion of the wafer in a vertical direction by greater than or equal to about 1 micrometer.
Claim 9 recites the planarizing of the lower surfaces of the plurality of first grooves comprises performing planarizing by at least a portion of a polishing apparatus having a rotation shaft in the vertical direction rotating inside the plurality of first grooves.
Claim 14 recites further comprising grinding a back surface of the wafer before the forming of the one or more internal cracks in the wafer.
Claim 19 recites a wavelength of a laser beam generated by the second laser device is shorter than a wavelength of a laser beam generated by the third laser device.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 January 19, 2026