DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0153] please correct “gate electrodes of the upper transistor UT1 and UT2” to “gate electrodes of the upper transistors UT1 and UT2”.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities: more clear wording should be used as described below-
“an upper surface of the plate layer on the plate layer “ would be clearer as “an upper surface of the plate layer”.
“a second semiconductor structure on the first semiconductor structure and
having a first region and a second region,” should be corrected to “a second semiconductor structure, having a first region and a second region, on the first semiconductor structure,”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1- 8, 10, 11, and 13-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Baek et al. US 20220231038.
Regarding claim 1, Baek discloses a semiconductor device, comprising:
a first semiconductor structure including a substrate (figure 13k, 201, [0035])
circuit devices on the substrate (figure 13k, 220, [0036], and circuit interconnection lines on the circuit devices (Figure 13k, 280);
and a second semiconductor structure on the first semiconductor structure (see figure 13k, where a second semiconductor structure CELL is on the first semiconductor structure PERI) and having a first region and a second region (figure 13k, R1 and R2, [0028]), wherein
the second semiconductor structure includes: a plate layer (figure 13k, 101 [0043])
gate electrodes including lower select gate electrodes (figure 13k, 130L [0051]) memory gate electrodes (figure 13k, 130M [0151]), and upper select gate electrodes (figure 13k, 130U [0151]) stacked in order and spaced apart from each other in a vertical direction perpendicular to an upper surface of the plate layer (see the positioning of the gate electrodes 130L and 130M relative to the substrate/plate layer 101 in figure 13k)
first channel structures (figure 13k, CH1 [0060]) penetrating through the lower select gate electrode and the memory gate electrodes and extending in the vertical direction, in the first region (see figure 13k, in the first region R1, the first channel structures CH1 extend in a vertical direction, penetrating the lower select gate electrode 130L and the memory gate electrodes 130M);
second channel structures (figure 13k, CH2 [0060]) penetrating through the upper select gate electrodes, extending in the vertical direction, and connected to the first channel structures, respectively, in the first region (see figure 13k, in the first region R1, the second channel structures CH2 extend in a vertical direction, penetrating the upper select gate electrodes 130U); and
contact plugs (figure 13k, 170 [0040]) penetrating through the gate electrodes, extending in the vertical direction, and electrically connecting the gate electrodes to a portion of the circuit interconnection lines, in the second region (see figure 13k - contact plugs 170 extend in the vertical direction, and electrically connect the gate electrodes 130 to a portion of the circuit interconnect lines 270 [0066 and 0160]) , wherein
the gate electrodes include first gate electrodes having a first thickness in the vertical direction in the first region and second gate electrodes having a second thickness in the vertical direction greater than the first thickness in the first region (Paragraph [0054] discloses that the gate electrodes 130 may have an increased thickness in the pad regions 130P, located in region 2, compared to the gate electrodes located in region 1.), and wherein
the second gate electrodes are commonly connected to one of the contact plugs (Paragraph [0066] discloses that one of the contact plugs 170 is connected to the second gate electrodes, i.e. to the gate electrodes in the pad regions of region 2) .
Regarding claim 2, Baek discloses the semiconductor device as claimed in claim 1, wherein the second gate electrodes include the upper select gate electrodes (see figure 13k where region 2 comprises upper select gate electrodes 130U) .
Regarding claim 3, Baek discloses the semiconductor device as claimed in claim 1, wherein: the first gate electrodes have a shape in which a thickness thereof is different at end regions thereof along a horizontal direction perpendicular to the vertical direction, and the second gate electrodes have a constant thickness. (The first gate electrodes comprise elements 131 and 131D [0074 and 0078], which have different thicknesses at the end region, as disclosed in paragraphs [0083-0084] where the first dummy gate electrodes 131D may have a wavy shape in the end regions, implying different thicknesses in these regions. The second gate electrodes 132 and 130U [0071] have a constant thickness, as seen in figure 13k.)
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Regarding claim 4, Baek discloses the semiconductor device as claimed in claim 1, wherein the first gate electrodes have the second thickness at end regions along a horizontal direction perpendicular to the vertical direction (See annotated figure 13k, where first gate electrodes 131 and 130L have different thicknesses in the horizontal direction.)
Regarding claim 5, Baek discloses the semiconductor device as claimed in claim 4, wherein the first gate electrodes are connected to the contact plugs in the end regions (figure 13k, contact plugs 170 to the first gate electrodes 131 and 130L [0160]).
Regarding claim 6, Baek discloses the semiconductor device as claimed in claim 1, wherein the second thickness is in a range of about 1.05 times to about 1.50 times the first thickness (Paragraph [0054] discloses that the second thickness may range from 150% to 210% of the first thickness, this corresponds to disclosing a second thickness of 1.5 times the first thickness – so, at 1.5 times, the value disclosed by Baek falls within the claimed range.)
Regarding claim 7, Baek discloses the semiconductor device as claimed in claim 1, wherein the second gate electrodes extend to a same length in a horizontal direction (Annotated figure 13K below shows that the second gate electrodes 130U and 132 extend to a same length in the horizontal direction as indicated by the length of the arrow extending to line A, note that some may extend further, but they at least extend to the same spot)
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Regarding claim 8, Baek discloses the semiconductor device as claimed in claim 1, wherein the first gate electrodes and the second gate electrodes include a same material (Paragraph [0055] discloses the all the gate electrodes 130, which comprise both the first and second gate electrodes, may include a single metal material, polycrystalline silicon, or a metal silicide material – therefore, all gate electrodes, comprising both first and second gate electrodes may include a same material from the disclosed list.)
Regarding claim 10, Baek discloses the semiconductor device as claimed in claim 1, wherein each of the contact plugs includes a vertical extension portion extending in the vertical direction and at least one horizontal extension portion extending horizontally from the vertical extension portion and in contact with one of the gate electrodes (Paragraph [0067] discloses wherein each of the contact plugs 170 may include a vertical extension portion 170V extending in the z direction and a horizontal extension portion 170H extending horizontally from the vertical extension portion 170V and in contact with the pad region gate electrode 130P).
Regarding claim 13 , Baek discloses a semiconductor device, comprising:
a plate layer (figure 13k, 101 [0043]);
gate electrodes (figure 13k, 130) stacked and spaced apart from each other in a vertical direction perpendicular to an upper surface of the plate layer on the plate layer (see the positioning of the gate electrodes 130 relative to the substrate/plate layer 101 in figure 13k)
channel structures (figure 13k, elements CH [0066]) penetrating through at least a portion of the gate electrodes and extending in the vertical direction (see figure 13k, where the channel structures CH penetrate through at least a portion of gate structures 130); and
contact plugs (figure 13k, 170 [0040]) penetrating through the gate electrodes, extending in the vertical direction, and electrically connected to the gate electrodes (see figure 13k - contact plugs 170 extend in the vertical direction, and electrically connect the gate electrodes 130 to a portion of the circuit interconnect lines 270 [0066]), wherein
the gate electrodes include first gate electrodes having a first thickness in the vertical direction and a second gate electrode having a second thickness in the vertical direction that is greater than the first thickness (Paragraph [0054] discloses that the gate electrodes 130 may have an increased thickness in the pad regions 130P, located in region 2, compared to the gate electrodes located in region 1.), and wherein,
among the gate electrodes, at least two gate electrodes including the second gate electrode are commonly connected to a first contact plug (Paragraph [0066] discloses that the second gate electrodes are commonly connected to one of the contact plugs 170. Also see annotated figure 13k below, where the first contact plug is commonly connected to at least two second gate electrodes 132 and 130U, as indicated.).
Regarding claim 14, Baek discloses the semiconductor device as claimed in claim 13, wherein the gate electrodes connected to the first contact plug extend to a same length in a horizontal direction perpendicular to the vertical direction (see the annotated figure 13k below, where the gate electrodes connected to the first contact plug, indicated by the callouts, extend to a same length in a horizontal direction, as indicated by the horizontal arrow.)
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Regarding claim 15 , Baek discloses the semiconductor device as claimed in claim 13, wherein: the first gate electrodes include regions having a third thickness in the vertical direction that is greater than the first thickness (The first gate electrodes comprise elements 131 and 131D [0074 and 0078], which have different thicknesses at the end region, as disclosed in paragraphs [0083-0084] where the first dummy gate electrodes 131D may have a wavy shape in the end regions, implying different thicknesses in these regions.) and the second gate electrode has the second thickness in an entire region The second gate electrodes 132 and 130U [0071] have a constant thickness, as seen in figure 13k.) .
Regarding claim 16 , Baek discloses the semiconductor device as claimed in claim 13, wherein the second gate electrode is an electrode of a string selection transistor or an erase transistor (Paragraph [0166 and 0167] discloses wherein the upper transistors may include a string select transistor and may also include an erase transistor. Therefore, the second gate electrode corresponding to these transistors may be the electrode of a string select or erase transistor.),
Regarding claim 17 , Baek discloses the semiconductor device as claimed in claim 13, wherein the first gate electrodes include gate electrodes of memory cells. (Paragraph [0164] discloses that the second (upper) semiconductor structure may be configured as a memory cell structure, so the first gate electrodes in this area would thus be gate electrodes of memory cells as illustrated in figure 14).
Regarding claim 18 , Baek discloses the semiconductor device as claimed in claim 13, wherein the gate electrodes connected to the first contact plug are gate electrodes sequentially disposed from an uppermost portion in a stack structure of the gate electrodes (see annotated figure 13k above, wherein the gate electrodes connected to the first contact plug, the indicated contact plug 170, are gate electrodes (130U) that are sequentially disposed from an uppermost portion in a stack structure of the gate electrodes ).
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Regarding claim 19, Baek discloses a data storage system, comprising: a semiconductor storage device including
a first semiconductor structure including circuit devices (figure 13k, 220, [0036]),
a second semiconductor structure on one surface of the first semiconductor structure and having first and second regions (see figure 13k, where a second semiconductor structure CELL is on the first semiconductor structure PERI) and having a first region and a second region (figure 13k, R1 and R2, [0028]), and
an input/output pad electrically connected to the circuit devices (figure 14, element 1101 is electrically connected to the circuit devices [0169]) ; and
a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device (In figure 14, the controller 1200 is connected to the semiconductor storage device 1000 through an input and output pad 1101, configured to control the semiconductor storage device [0169]), wherein
the second semiconductor structure includes: a plate layer (figure 13k, 101 [0043]);
gate electrodes (figure 13k, 130) stacked and spaced apart from each other in a vertical direction perpendicular to an upper surface of the plate layer on the plate layer (see the positioning of the gate electrodes 130 relative to the substrate/plate layer 101 in figure 13k);
channel structures (figure 13k, elements CH [0066]) penetrating through at least a portion of the gate electrodes and extending in the vertical direction (see figure 13k, where the channel structures CH penetrate through at least a portion of gate structures 130); and
contact plugs (figure 13k, 170 [0040]) penetrating through the gate electrodes, extending in the vertical direction, and electrically connected to the gate electrodes (see figure 13k - contact plugs 170 extend in the vertical direction, and electrically connect the gate electrodes 130 to a portion of the circuit interconnect lines 270 [0066]), wherein
the gate electrodes include first gate electrodes having a first thickness in the vertical direction in the first region and second gate electrodes having a second thickness in the vertical direction and that is greater than the first thickness in the first region thickness (Paragraph [0054] discloses that the gate electrodes 130 may have an increased thickness in the pad regions 130P, located in region 2, compared to the gate electrodes located in region 1.), and wherein,
among the gate electrodes, at least two gate electrodes including the second gate electrode are commonly connected to a first contact plug (Paragraph [0050] discloses wherein the contact plugs 170 may be connected to different gate electrodes 130, implying that at least two gate electrodes 130 are commonly connected to at least one contact plug 170. Figure 13k illustrates that one of these connected gate electrodes may be second gate electrode 132).
Regarding claim 20, Baek discloses the data storage system as claimed in claim 19, wherein the gate electrodes connected to the first contact plug surround a side surface of the first contact plug (Figure 13k discloses first contact plug 170, surrounded on side surfaces by the gate electrodes130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Billingsley et al. US 20220068945.
Regarding claim 9, Baek discloses the semiconductor device as claimed in claim 1.
Baek lacks wherein the first channel structures and the second channel structures are laterally misaligned from each other in a horizontal direction.
However, Billingsley discloses a memory cell array wherein the first channel structures (figure 6, element 59) and the second channel structures (figure 6, element 39) are laterally misaligned from each other in a horizontal position (paragraph [0023] and illustrated in figures 6 and 7).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to alter the first channel structures and the second channel structures of Baek to be misaligned from each other in the horizontal direction in order to improve the structural stability of the device.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Baek.
Regarding claim 11 , Baek, in the embodiment of figure 13k, discloses the semiconductor device as claimed in claim 10.
Baek, in the embodiment of figure 13k, lacks wherein: the contact plug connected to the second gate electrodes includes a plurality of horizontal extension portions, and lengths of the plurality of horizontal extension portions in a horizontal direction are equal to each other.
However, in another embodiment (illustrated in figure 11), Baek discloses wherein the contact plug connected to the second gate electrodes includes a plurality of horizontal extension portions, and lengths of the plurality of horizontal extension portions in a horizontal direction are equal to each other, as shown in the annotated figure 11 below, where there are two extension portions of similar size. However, MPEP 2144.04 IV states:
IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
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Therefore, it would have been obvious to a person of ordinary skill in the art before the effective date of filing to add more horizontal extension portions to the contact plugs in order to increase the number and density of possible electrical connections, and to make these horizontal extension regions the same size in order to simplify the design of the device.
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Regarding claim 12, Baek, in the embodiment of figure 13k, discloses the semiconductor device as claimed in claim 1, wherein: in the second region, the gate electrodes form a downward first step structure of which a level decreases in the vertical direction and the contact plugs penetrate through the first step structure (shown by callouts in annotated figure 3k).
Baek, in the embodiment of figure 13k, lacks an upward second step structure of which a level increases in the vertical direction.
However, in another embodiment (illustrated in figure 11 [0110-0112], Baek discloses a similar structure also comprising an upward second step structure as indicated in annotated figure 11 below.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective date of filing to add an upward second step structure of the gate electrodes as in the embodiment of figure 11 in order to create more steps in a smaller space, thereby improving efficiency, reducing manufacturing complexity and cost, and improving the structural integrity of the stacks.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure US 20210242128 Ito discloses various step configurations of the gate stacks, US 20210408032 to Baraskar and US 20220189984 Okina disclose similar memory array, different assignee, and US 20220139943 to Go discloses contact plugs with multiple extensions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 8 am- 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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