Office Action Predictor
Last updated: April 15, 2026
Application No. 18/519,568

SEMICONDUCTOR MODULE

Non-Final OA §103
Filed
Nov 27, 2023
Examiner
BOWEN, ADAM S
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., LTD.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
1y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
678 granted / 704 resolved
+28.3% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
21 currently pending
Career history
725
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 704 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/27/2023 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Rengarajan et al. (2019/0221449) in view of the following reasons. Re claim 1, Rengarajan teaches a semiconductor module (Fig. 1) comprising: a semiconductor unit (100) including a semiconductor chip (20); a housing (7) for accommodating the semiconductor unit (100); and a target member bonded to the housing by an adhesive [16]. Rengarajan does not explicitly teach the adhesive having a water absorption rate of 0.5% or less. However, Applicant has not shown wherein the adhesive having a water absorption rate of 0.5% or less has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the water absorption rate of the adhesive so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 2, Rengarajan teaches the semiconductor module according to claim 1, wherein the target member includes a base on which the semiconductor unit is disposed [15-19], and wherein the housing and the base are bonded to each other by a first adhesive [16] having a water absorption rate of 0.5% or less (see rejection of claim 1). Re claim 3, Rengarajan teaches the semiconductor module according to claim 2, wherein the base has a surface having a region bonded to the housing [16-19], wherein the housing has a surface bonded to the base, and wherein the region of the base [16-22], the surface of the housing, or both the region of the base and the surface of the housing have a groove for accommodating the first adhesive [16-22]. Re claim 4, Rengarajan teaches the semiconductor module according to claim 1, wherein the target member includes a connection terminal (4) electrically connected to the semiconductor unit [20], and wherein the housing and the connection terminal are bonded to each other by a second adhesive [16, 19] having a water absorption rate of 0.5% or less (see rejection of claim 1). Re claim 5, Rengarajan teaches the semiconductor module according to claim 4, wherein the housing (7) has a terminal surface having a terminal hole (Fig. 1), the terminal hole having an inner wall surface (Fig. 1), wherein the connection terminal protrudes from an inside of the terminal hole toward an outside of the terminal surface (Fig. 1), the connection terminal having an outer wall surface [20-21], and wherein the second adhesive [16, 19] is accommodated in a space between the inner wall surface of the terminal hole and the outer wall surface of the connection terminal (Fig. 1). Allowable Subject Matter Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 6, Rengarajan teaches the semiconductor module according to claim 5, yet remains explicitly silent to wherein a diameter of the terminal hole at a first position at which the terminal surface is present is greater than a diameter of the terminal hole at a position separated in a depth direction from a position of the terminal surface. Claims 7-8 are objected to for at least depending from objected claim 6. Re claim 9, Rengarajan teaches the semiconductor module according to claim 1, yet remains explicitly silent to wherein the target member includes a first connection terminal and a second connection terminal that are electrically connected to the semiconductor unit, wherein the housing has a terminal surface having a recess, wherein the recess has a bottom surface, the bottom surface having a first terminal hole and a second terminal hole, wherein the first connection terminal protrudes from an inside of the first terminal hole toward an outside of the terminal surface, wherein the second connection terminal protrudes from an inside of the second terminal hole toward the outside of the terminal surface, and wherein the recess accommodates a second adhesive having a water absorption rate of 0.5% or less. Re claim 10, Rengarajan teaches the semiconductor module according to claim 1, yet remains explicitly silent to further comprising an auxiliary member, the auxiliary member having a first surface and a second surface, wherein the target member includes a first connection terminal and a second connection terminal that are electrically connected to the semiconductor unit, wherein the housing has a terminal surface, the terminal surface having a first terminal hole and a second terminal hole, wherein the first surface is bonded to the terminal surface by an adhesive having a water absorption rate of 0.5% or less, wherein the auxiliary member includes: a first recess and a second recess that are on the second surface; a first communication hole causing the first recess and the first terminal hole to be in communication with each other; and a second communication hole causing the second recess and the second terminal hole to be in communication with each other, wherein the first connection terminal protrudes from an inside of the first terminal hole toward an outside of the second surface via the first communication hole, wherein the second connection terminal protrudes from an inside of the second terminal hole toward the outside of the second surface via the second communication hole, and wherein the first recess and the second recess accommodate a second adhesive having a water absorption rate of 0.5% or less. Re claim 11, Rengarajan teaches the semiconductor module according to claim 1, yet remains explicitly silent to wherein the target member includes: a base on which the semiconductor unit is disposed; and a connection terminal electrically connected to the semiconductor unit, wherein the housing and the base are bonded to each other by a first adhesive having a water absorption rate of 0.5% or less, wherein the housing and the connection terminal are bonded to each other by a second adhesive having a water absorption rate of 0.5% or less, and wherein a viscosity of the first adhesive before being cured is greater than a viscosity of the second adhesive before being cured. Re claim 12, Rengarajan teaches the semiconductor module according to claim 1, yet remains explicitly silent to wherein the housing includes a frame-shaped side wall portion surrounding the semiconductor unit, wherein the target member includes a lid for closing an opening of the side wall portion, and wherein the housing and the lid are bonded to each other by a third adhesive having a water absorption rate of 0.5% or less. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /ADAM S BOWEN/Examiner, Art Unit 2897
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Prosecution Timeline

Nov 27, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §103
Apr 01, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+2.5%)
1y 8m
Median Time to Grant
Low
PTA Risk
Based on 704 resolved cases by this examiner. Grant probability derived from career allow rate.

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