DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 4-6, 11, 12, and 14-16 have been amended.
Claims 3 and 13 have been cancelled.
Claims 21-32 have been added.
Claims 1-5, 11-15, and 21-32 have been examined.
The specification objections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 11, 15, 23, 25, 26, 29, 31, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2010/0199074 by Gemmeke et al. (hereinafter referred to as “Gemmeke”) in view of US Publication No. 2020/028865 by Langhammer et al. (hereinafter referred to as “Langhammer”).
Regarding claims 1 and 11, taking claim 1 as representative, Gemmeke discloses:
a processor comprising: an instruction decoder configured to decode an instruction (Gemmeke discloses, at Figure 1 and related description, a processor with a decoder, which discloses decoding an instruction.);
an arithmetic circuit configured to execute the instruction and output operation result data (Gemmeke discloses, at Figure 1 and related description, execution units, which discloses an arithmetic circuit to execute instructions and output result data.);
an instruction queue configured to hold the instruction; and an instruction fetch circuit configured to fetch the instruction held in the instruction queue and supply the instruction to the instruction decoder (Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses an instruction queue and fetching instructions therefrom to supply to the instruction decoder.),
wherein the instruction held in the instruction queue includes an instruction code, an operand … (Gemmeke discloses, at Figure 2 and related description, instructions that have opcodes and operands.), and
wherein the instruction fetch circuit fetches and supplies the instruction to the instruction decoder… (Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses the instruction fetch circuit fetches and supplies the instruction to the instruction decoder.).
Gemmeke does not explicitly disclose the aforementioned instruction also includes insertion prohibition information, the insertion prohibition information is stored in an area separate from the instruction code and the operand, and the aforementioned fetching and supplying are in response to detecting that the insertion prohibition information included in the instruction fetched from the instruction queue indicates that an insertion is prohibited.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
instructions including insertion prohibition information stored in an area separate from the instruction code and the operand (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in a dedicated field in an instruction word that specifies whether to insert NOPs, which discloses including insertion prohibition information stored in an area separate from the instruction code and the operand.), and
supplying instructions in response to detecting that the insertion prohibition information included in the instruction indicates that insertion is prohibited (Langhammer discloses, at Figures 5 and 6 and related description, that when NOP insertion is disabled, instructions are processed, which discloses supplying instructions in response to detecting that the insertion prohibition information included in the instruction indicates that insertion is prohibited.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the bubble insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Regarding claims 5 and 15, taking claim 5 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
…executing an operation by using the operation result data bypassed from the arithmetic circuit …, and …executing an operation without using the operation result data bypassed from the arithmetic circuit … (Gemmeke discloses, at Figure 3 and related description, selecting between providing data from register 308 (no bypass) or from madd instruction 304 (bypass), which discloses selecting between using bypassed result data or not.).
Gemmeke does not explicitly disclose insertion prohibition information included in the instruction for indicating that the insertion is prohibited and insertion prohibition information included in the instruction for indicating that the insertion is permitted.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
wherein the instruction includes insertion prohibition information indicating that an insertion between a preceding instruction immediately before the instruction and the instruction in an instruction pipeline is prohibited or permitted (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in an instruction that specifies whether to insert NOPs, which discloses indicating whether insertion is prohibited or permitted.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Regarding claims 23 and 29, taking claim 23 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
a first selector configured to select the data held in the data holding circuit or the operation result data and output the selected data or the selected operation result data to the arithmetic circuit (Gemmeke discloses, at Figure 3 and related description, selecting between providing data from register 308 (no bypass) or from madd instruction 304 (bypass), which discloses a selector to select based on the bypass control signal.).
Regarding claims 25 and 31, taking claim 25 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke does not explicitly disclose the insertion prohibition information indicates that the insertion of at least one of a bubble or a no-operation instruction between a preceding instruction before the instruction and the instruction in an instruction pipeline is prohibited or permitted.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
insertion prohibition information indicates that the insertion of at least one of a bubble or a no-operation instruction between a preceding instruction before the instruction and the instruction in an instruction pipeline is prohibited or permitted (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in an instruction that specifies whether to insert NOPs, which discloses indicating whether bubble insertion is prohibited or permitted.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the bubble insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Regarding claims 26 and 32, taking claim 26 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke does not explicitly disclose the insertion prohibition information indicates that the insertion of at least one of a bubble or a no-operation instruction between a preceding instruction immediately before the instruction and the instruction in an instruction pipeline is prohibited or permitted.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
insertion prohibition information indicates that the insertion of at least one of a bubble or a no-operation instruction between a preceding instruction immediately before the instruction and the instruction in an instruction pipeline is prohibited or permitted (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in an instruction that specifies whether to insert NOPs, which discloses indicating whether bubble insertion is prohibited or permitted. See also ¶ [0040], which discloses consecutive instructions, i.e., immediately preceding.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the bubble insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gemmeke in view of Langhammer in view of US Publication No. 2004/0239397 by Mudge et al. (hereinafter referred to as “Mudge”).
Regarding claims 2 and 12, taking claim 2 as representative, Gemmeke discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
a latch configured to hold the operation result data (Gemmeke discloses, at Figure 4 and related description, storing output data, which discloses a latch to do so, e.g., register 404.); and
a second selector arranged between an output of the arithmetic circuit and the latch and configured to connect the output of the arithmetic circuit… to an input of the latch based on a hold control signal (Gemmeke discloses, at Figure 4 and related description, selectively coupling output of an arithmetic circuit, e.g., result at 306, to a latch, e.g., register 404, which discloses a second selector and selecting based on a hold control signal.),
wherein the instruction decoder generates the hold control signal for …a subsequent instruction to be executed using the operation result data bypassed from the arithmetic circuit based on an execution of the preceding instruction (Gemmeke discloses, at Figure 1 and related description, decoding instructions, which discloses generating the hold control signal. Gemmeke also discloses, at Figure 4 and related description, bypassing result data based on execution of a preceding instruction for use by a subsequent instruction.).
Gemmeke does not explicitly disclose selectively coupling an output of the latch to the latch and an insertion cycle, in response to detecting that the insertion has occurred between a preceding instruction and the aforementioned subsequent instruction.
However, in the same field of endeavor (e.g., instruction processing) Mudge discloses:
coupling the output of a latch to the input of the latch and insertion (Mudge discloses, at Figure 20 and related description, coupling the output of a latch, e.g., the Razor FFs, to the input and inserting bubbles.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the configuration disclosed by Mudge in order to improve performance by preventing erroneous values from propagating down the pipeline.
Claims 4, 14, 21, 22, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Gemmeke in view of Langhammer in view of US Publication No. 2017/0075622 by Kwon et al. (hereinafter referred to as “Kwon”).
Regarding claims 4 and 14, taking claim 4 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
…the instruction fetch circuit fetches the instruction from the instruction queue and supplies the instruction to the instruction decoder…(Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses fetching and supplying to the decoder.).
Gemmeke does not explicitly disclose in response to detecting that the insertion prohibition information included in the instruction indicates that the insertion is permitted, the instruction fetch circuit supplies a no-operation instruction to the instruction decoder until an amount of the instructions held in the instruction queue becomes greater than or equal to a first threshold value upon detecting the amount of the instructions held in the instruction queue is less than the first threshold value, and the aforementioned fetch and supply is performed upon detecting the amount of the instructions held in the instruction queue becomes greater than or equal to the first threshold value.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
in response to detecting that the insertion prohibition information included in the instruction indicates that the insertion is permitted, the instruction fetch circuit supplies a no-operation instruction to the instruction decoder… (Langhammer discloses, at Figures 5 and 6 and related description, inserting NOPs when indicated by the instruction’s delay information.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Also in the same field of endeavor (e.g., instruction processing) Kwon discloses:
adjusting reading based on determining the amount of data in a queue relative to a threshold (Kwon discloses, at ¶ [0075], a first scheduling scheme when the queue is below a threshold fullness and a second scheduling scheme when the queue is above a threshold fullness, which discloses switching in response to the fullness relative to a threshold.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the queue fullness threshold as disclosed by Kwon in order to improve performance by preventing data loss or stalls due to limited queue capacity.
Regarding claims 21 and 27, taking claim 21 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
the instruction fetch circuit determines whether to supply the instruction to the instruction decoder…(Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses the instruction fetch circuit determines whether to supply the instruction to the instruction decoder.).
Gemmeke does not explicitly disclose the aforementioned determining is based on an amount of instructions held in the instruction queue and the insertion prohibition information included in the instruction.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
determining based on insertion prohibition information in the instruction (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in a dedicated field in an instruction word that specifies whether to insert NOPs, which discloses including insertion prohibition in an instruction.), and
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the bubble insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Also in the same field of endeavor (e.g., instruction processing) Kwon discloses:
determining based on an amount of data in a queue relative to a threshold (Kwon discloses, at ¶ [0075], a first scheduling scheme when the queue is below a threshold fullness and a second scheduling scheme when the queue is above a threshold fullness, which discloses switching in response to the fullness relative to a threshold.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the queue fullness threshold as disclosed by Kwon in order to improve performance by preventing data loss or stalls due to limited queue capacity.
Regarding claims 22 and 28, taking claim 22 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
the instruction fetch circuit supplies the instruction to the instruction decoder …(Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses the instruction fetch circuit the instruction fetch circuit supplies the instruction to the instruction decoder.).
Gemmeke does not explicitly disclose the aforementioned supplying is in response to determining that an amount of instructions held in the instruction queue is greater than or equal to a threshold value, the threshold value being set greater than or equal to a maximum number of consecutive instructions that require bypass of operation result data.
However in the same field of endeavor (e.g., instruction processing) Kwon discloses:
determining based on an amount of data in a queue relative to a threshold (Kwon discloses, at ¶ [0075], a first scheduling scheme when the queue is below a threshold fullness and a second scheduling scheme when the queue is above a threshold fullness, which discloses switching in response to the fullness relative to a threshold, which discloses an amount of instructions held in the instruction queue is greater than or equal to a threshold value, the threshold value being set greater than or equal to a maximum number of consecutive instructions that require bypass of operation result data.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the queue fullness threshold as disclosed by Kwon in order to improve performance by preventing data loss or stalls due to limited queue capacity.
Regarding claims 24 and 30, taking claim 24 as representative, Gemmeke, as modified, discloses the elements of claim 1, as discussed above. Gemmeke also discloses:
the instruction fetch circuit supplies …[an] instruction to the instruction decoder…(Gemmeke discloses, at Figure 1 and related description, fetch and decode stages, which discloses the instruction fetch circuit determines whether to supply the instruction to the instruction decoder.).
Gemmeke does not explicitly disclose the aforementioned instruction is a no-operations and the aforementioned supplying based on the insertion prohibition information and an amount of instructions held in the instruction queue.
However, in the same field of endeavor (e.g., instruction processing) Langhammer discloses:
determining based on insertion prohibition information in the instruction and supplying NOPs (Langhammer discloses, at Figures 5 and 6 and related description, including delay information in a dedicated field in an instruction word that specifies whether to insert NOPs, which discloses including insertion prohibition in an instruction.), and
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the bubble insertion as disclosed by Langhammer in order to improve performance by providing and efficient way to mitigate hazards. See, e.g., Langhammer, ¶ [0003].
Also in the same field of endeavor (e.g., instruction processing) Kwon discloses:
determining based on an amount of data in a queue relative to a threshold (Kwon discloses, at ¶ [0075], a first scheduling scheme when the queue is below a threshold fullness and a second scheduling scheme when the queue is above a threshold fullness, which discloses switching in response to the fullness relative to a threshold.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gemmeke to include the queue fullness threshold as disclosed by Kwon in order to improve performance by preventing data loss or stalls due to limited queue capacity.
Response to Arguments
On pages 13-14 of the response filed November 12, 2025 (“response”), the Applicant argues, “Claim 1 is amended to include the limitations recited in previous claim 3. The Office Action on pages 5 and 6 concedes that Gemmeke does not explicitly disclose the feature recited in previous claim 3. … Hence, Gemmeke does not anticipate claim 1.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. As indicated in the rejection of previous claim 3, the claims are unpatentable over Gemmeke in view of Langhammer.
On page 15 of the response the Applicant argues, “The Office Action on page 6 appears to equate the delay bits of Langhammer with the bubble insertion prohibition information recited in previous claims 3 and 13…. As is described above and illustrated in FIGS. 6A, 6B, and 6C, the delay field containing the instruction delay bits is included in some dedicated or unused portion of the operand, is included in some dedicate or unused portion of the opcode, or straddle the boundary between the opcode and the operand. Thus, the delay bits are included in an area inside the operand or the opcode. Nowhere in the specification and drawings, does Langhammer teach or suggest the feature of "the insertion prohibition information is stored in an area separate from the instruction code and the operand" recited in amended claims 1 and 11. Thus the noted feature of claims 1 and 11 distinguishes over Langhammer.”
Though fully considered, the Examiner respectfully disagrees. The claims say that the insertion information is included in the instruction. This is qualified as being in the instruction, but not in an instruction code or an operand. The claim is interpreted as including the insertion information in the instruction word, which also includes bits for an instruction code and bits for an operand, such as a source or destination register. See also, e.g., Applicant’s Figure 5.
Langhammer inarguably discloses including the delay information in a delay field in the instruction word. See, e.g., ¶ [0042]. In Langhammer, the instruction word includes only two portions, the opcode portion and the operand portion. See, e.g., ¶ [0045]. Given the delay field is located in the instruction word, the delay field must be included in the opcode portion, the operand portion, or both. In fact, Langhammer discloses all three possibilities. See ¶ [0046]. Langhammer explains that the operand portion can include what are traditionally called operands, such as source and destination registers. In addition to the source and destination information, the operand portion can also include other information, such as immediate values, etc. Lanhagmmer discloses including dedicated delay field in this otherwise unused space in the instruction word. See, e.g., ¶ [0041]. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 16-17 of the response the Applicant argues the remaining claims are not disclosed for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The reasons set forth in the remarks and rejections presented above, including those regarding the independent claims, are applicable to these claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183