DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species 1, claims 1-3 and 8-21 readable thereon, in the reply filed on 20 March 2026 is acknowledged.
The traversal is on the ground(s) that there will not be a search burden. This is not found persuasive because the standard for restriction is whether the inventions are independent or distinct and if there is a search burden. Burden was established in the restriction requirement (pg. 2-3, 4-5); burden was established on the basis of different fields of search, different search queries, and the separate status acquired in the art by distinct inventions in view of separate classifications. Applicant has failed to set forth evidence establishing the distinct inventions/species would have the same field of search, the same search queries, or the same classification. The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the resin layer, which is not in contact with the plurality of monitor lenses and has a flat top (as presented in claim 8), a display device comprising a final product of the semiconductor device of claim 15 (as independently presented in claims 16 and 21), a display unit including a final product of the semiconductor device of claim 15 (as independently presented in claim 17 and 18), a light source including a final product of the semiconductor device of claim 15 (as presented in claim 19), and a lighting appliance including a final product of the semiconductor device of claim 15 (as presented in claim 20) must be shown or the features canceled from the claims. The semiconductor device including the features of a pixel region and a monitor region are shown in the drawings as a component of an intermediate un-diced semiconductor wafer; the final product of the semiconductor device including claimed features is not represented in the drawings. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yomori (US PGPub 20130087874 A1; hereinafter referred to as “Yomori”).
Re claim 1: Yomori teaches a semiconductor device (FIG. 2: el. 201; para. 33; FIG. 3A, 3B, 3C: el. 300; para. 38) that comprises, on a substrate (FIG. 3A: el. 301), a pixel region where a plurality of pixels are arranged (FIG. 1A, 2: el. 202, 104; para. 33; FIG. 3A), and a monitor region (FIG. 1A, 2: el. 204; para. 33), wherein in the pixel region, a plurality of lenses (FIG. 3A: el. 105; para. 33) are arranged on an underlayer (FIG. 3A: el. 305, 306; para. 38) such that the underlayer is not exposed (FIG. 3A), in the monitor region, a plurality of monitor lenses (FIG. 3B, 1B: el. 115; para. 36, 41) are arranged on the underlayer, and the plurality of monitor lenses include a pair of monitor lenses arranged such that the underlayer is not exposed between two monitor lenses adjacent to each other (FIG. 3B, 1B: el. 115). This embodiment of Yomori fails to teach a pair of monitor lenses arranged with an exposed portion where the underlayer is exposed between two monitor lenses adjacent to each other.
An additional embodiment of Yomori teaches configurations including multiple types of monitor structures (para. 61, 67-69) and including a pair of monitor lenses arranged with an exposed portion where the underlayer is exposed between two monitor lenses adjacent to each other (FIG. 7C; para. 67). Yomori also teaches a benefit of multiple types of monitor structures including a pair of monitor lenses arranged with an exposed portion between two monitor lenses is a reduction in measurement time and measurement error (para. 67, 69) and an increase in the number of compatible characterization tools (para. 67).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of the embodiments of Yomori to enable using a configuration including multiple types of monitor structures including a pair of monitor structures where the underlayer is exposed between the pair in the monitor region of the semiconductor device of Yomori, for the benefit of a reduced measurement time and measurement error along with an increased number of compatible characterization tools.
Re claim 2: Yomori teaches the semiconductor device according to claim 1, wherein the plurality of lenses in the pixel region are arranged at a predetermined pitch (FIG. 1A: el. W, 105; para. 35), and an arranging interval of two monitor lenses, among the plurality of monitor lenses, adjacent to each other arranged such that the underlayer is not exposed is equal to the predetermined pitch (FIG. 1B: el. W, 115; para. 37).
Re claim 11: Yomori teaches the semiconductor device according to claim 1, wherein a color filter layer is arranged between the substrate and the plurality of monitor lenses (FIG. 3B: el. 305; para. 38).
Re claim 12: Yomori teaches the semiconductor device according to claim 11, wherein the underlayer includes the color filter layer (FIG. 3B: el. 305, 306|underlayer includes planarization layer 306 and color filter layer 305).
Re claim 13: Yomori teaches the semiconductor device according to claim 1, wherein the underlayer includes a planarizing layer used to planarize a surface of a layer below the underlayer (FIG. 3B: el. 306; para. 38|underlayer includes planarization layer 306 and color filter layer 305).
Re claim 14: Yomori teaches the semiconductor device according to claim 1, wherein at least one of the plurality of pixels each include a photoelectric conversion element (FIG. 3A: el. 307; para. 38).
Claims 3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yomori as applied to claims 1 and 2 above, and further in view of Tsuruta (JP 2007173535 A; hereinafter referred to as “Tsuruta”).
Re claim 3: Yomori fails to teach the semiconductor device according to claim 2, wherein an arranging interval of two monitor lenses, among the plurality of monitor lenses, adjacent to each other via the exposed portion is larger than the predetermined pitch.
In a similar field of endeavor, Tsuruta teaches a semiconductor device comprising: a plurality of lenses arranged at a predetermined pitch in a pixel region (FIG. 1: el. 14a; para. 9) and a plurality of monitor lens arranged at the predetermined pitch in a monitor region (FIG. 1: el. 14b; para. 10), and the plurality of monitor lenses include a pair of monitor lenses arranged with an exposed portion formed by omitting a lens in the lens array (FIG. 1: el. 14b; para. 11). Tsuruta teaches an arranging interval of two monitor lenses, among the plurality of monitor lenses, adjacent to each other via the exposed portion is larger than the predetermined pitch (FIG. 1: el. 14b; para. 11). Tsuruta also teaches that a benefit of forming a monitor lens array in the peripheral dummy region as an extension of the lens array in the pixel region is improved quality of the lenses of the pixel region without increasing manufacturing costs (para. 10, 15). Tsuruta further teaches a benefit of omitting a lens of the monitor lens array is that the omitted lens can be used as an identifiable monitoring aid for determining/indexing position during microscopic inspection of the lens array (para. 5, 11).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Yomori and Tsuruta, to enable using a monitor lens array as an extension of a pixel lens array of Tsuruta in the peripheral and monitoring regions of the semiconductor device of Yomori, for the benefit of improved pixel lens array quality without increased manufacturing costs and the benefit of providing an easily identifiable reference position for characterization tools.
Re claim 9: The combination of Yomori and Tsuruta teaches the semiconductor device according to claim 1, wherein the plurality of monitor lenses include a monitor lens not in contact with the exposed portion (Yomori - FIG. 3B: el. 115|monitor lenses in the center of FIG. 3B are not in contact with an exposed portion where the underlayer is exposed between two monitor lenses adjacent to each other) (Tsuruta – FIG. 1: el. 14b|additionally Tsuruta teaches monitor lenses formed in the peripheral area as an extension of the pixel lens array and including monitor lenses fully surrounded by other monitor lenses (in contrast to the monitor lenses which border an omitted lens).
Re claim 10: The combination of Yomori and Tsuruta teaches the semiconductor device according to claim 1, further comprising a dummy pixel region where a dummy pixel is arranged on the substrate so as to be adjacent to the pixel region (Tsuruta - para. 9, 10|peripheral region adjacent to pixel region includes: the optical black region which is a dummy pixel region including photoelectric conversion elements but not forming a pixel of the device), wherein the monitor region is arranged in the dummy pixel region (Tsuruta – FIG. 1: el. 14, 15; para. 9|microlens layer 14 includes monitor lens array 14b formed across the peripheral area 15 and thus the monitor region is arranged in the dummy pixel region of the peripheral area).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yomori as applied to claim 1 above, and further in view of Yang et al. (US PGPub 20220013564 A1; hereinafter referred to as “Yang”).
Re claim 8: Yomori fails to teach the semiconductor device according to claim 1, wherein a resin layer, which is not in contact with the plurality of monitor lenses and has a flat top, is arranged in the monitor region, and the resin layer is formed of the same material as the plurality of lenses.
In a similar field of endeavor, Yang teaches a semiconductor device comprising: a plurality of lenses arranged at a predetermined pitch in a pixel region (FIG. 1: el. ML; para. 31), a plurality of monitor lens arranged at the predetermined pitch in a monitor region (FIG. 1: el. DML; para. 31), and a plurality of finger structures (FIG. 1,2: el. 136; para. 31) adjacent to the monitor lenses which are formed as extended structures with a flat top without curvature in the extension direction (para. 7, 31). Yang teaches a semiconductor device, wherein a resin layer (FIG. 2: el. 136), which is not in contact with the plurality of monitor lenses (FIG. 2: el. DML) and has a flat top (FIG. 2: el. 136; para. 7| fingers formed as extended structures with a flat top without curvature in the extension direction), is arranged in the monitor region (FIG. 2: el. 200|monitor region formed outside of the pixel region 100), and the resin layer is formed of the same material as the plurality of lenses (para. 39). Yang further teaches a benefit of the finger structures is to provide a structure which increases adhesion of protective capping layers and prevents a protective lens capping layer from being easily peeled up (para. 23, 28).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Yomori and Yang, to enable using the resin layer of Yang in the monitor region of the semiconductor device of Yomori, for the benefit of protecting the lenses by enabling a protective lens capping layer with improved adhesion.
Claims 15-21 are rejected under 35 U.S.C. 103 as being unpatentable over Yomori as applied to claim 1 above, and further in view of Sano et al. (US PGPub 20210273203 A1; hereinafter referred to as “Sano”).
Re claim 15: Yomori teaches the semiconductor device according to claim 1, wherein the semiconductor device can be a display device (para. 69). However, Yomori fails to teach the integration of display components into the semiconductor device; Yomori fails to directly disclose the semiconductor device of claim 1, wherein at least one of the plurality of pixels each include a light emitting element.
In a similar field of endeavor, Sano teaches a semiconductor device including both a pixel region and a microlens and also teaches a display device formed from the semiconductor device (para. 1). Sano teaches a semiconductor device, wherein at least one of the plurality of pixels (FIG. 1A: el. 107, 108a; para. 44-45|pixel formed from light emitting area 108a between pixel separation film 107 regions) each include a light emitting element (FIG. 1A: el. 102; para. 44).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Yomori and Sano, to enable using the light emitting element of the pixels of Sano in the pixels of the semiconductor device of Yomori, for the benefit of simplifying manufacturing by using a known configuration for forming a display device including a semiconductor device with a microlens and a pixel region.
Re claim 16: The combination of Yomori and Sano teaches a display device comprising the semiconductor device according to claim 15, and an active element connected to the semiconductor device (Sano - para. 87|switching element such as a transistor attached to light emitting element of the semiconductor device).
Re claim 17: The combination of Yomori and Sano teaches a photoelectric conversion device (Sano - FIG. 10A: el. 1100; para. 125) comprising an optical unit including a plurality of lenses, an image sensor configured to receive light having passed through the optical unit (Sano - para. 122-124), and a display unit configured to display an image, wherein the display unit displays an image captured by the image sensor, and includes the semiconductor device according to claim 15 (Sano - para. 115, 122-124).
Re claim 18: The combination of Yomori and Sano teaches an electronic apparatus (Sano - FIG. 10B: el. 1200; para. 126) comprising a housing (Sano - FIG. 10B: el. 1203) provided with a display unit (Sano - FIG. 10B: el. 1201), and a communication unit provided in the housing and configured to perform external communication, wherein the display unit includes the semiconductor device according to claim 15 (Sano - para. 126, 115).
Re claim 19: The combination of Yomori and Sano teaches an illumination device (Sano - FIG. 12A: el. 1400; para. 131) comprising a light source (Sano - FIG. 12A: el. 1402; para. 131), and at least one of a light diffusing unit and an optical film (Sano - FIG. 12A: el. 1405; para. 131), wherein the light source includes the semiconductor device according to claim 15 (Sano - para. 115, 131).
Re claim 20: The combination of Yomori and Sano teaches a moving body (Sano - FIG. 12B: el. 1500; para. 134-137) comprising a main body (Sano - FIG. 12B: el. 1503; para. 136), and a lighting appliance provided in the main body, wherein the lighting appliance includes the semiconductor device according to claim 15 (Sano - FIG. 12B: el. 1501; para. 134-135, 115).
Re claim 21: The combination of Yomori and Sano teaches a wearable device characterized by comprising a display device (Sano - FIG. 13B: el. 1610, 1612) configured to display an image, wherein the display device includes the semiconductor device according to claim 15 (Sano - para. 141-144, 115).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898