Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 06/10/2026, in which: claims 1-3, 5, 6, 8 and 9 are amended; and the rejection of the claims are traversed. Claims 1-9 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1-9 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feuerbaum et al, US 20220189855 in view of Boettcher et al, US 20190189545.
Regarding claim 1, Feuerbaum discloses : A semiconductor module comprising: a semiconductor chip arranged on a substrate(Fig. 10, #1010 on #1006); and a wiring member electrically connected to the semiconductor chip(#1014), wherein the wiring member includes: a body portion elongated in a first direction(#1024) and including a plurality of flat plate- shaped portions that include a first end portion(#1030), a second end portion(#1020) and an extending portion that extends in the first direction between the first end portion and the second end portion(#1024);
Feuerbaum does not disclose : at least two ridges protruding from at least two surfaces of at least two flat plate-shaped portions among the plurality of flat plate-shaped and extending along the first direction.
However, in the same field of endeavor, Boettcher teaches : at least two ridges protruding from at least two surfaces of at least two flat plate-shaped portions among the plurality of flat plate-shaped and extending along the first direction(Fig. 4a-4b, #426b and #426c may be in locations #218 and #214).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Boettcher to Feuerbaum to provide structural integrity to a wiring member (Boettcher [0014]).
Regarding claim 9, Feuerbaum discloses : A wiring member electrically connected to a semiconductor chip, the wiring member comprising: a body portion elongated in a first direction and including a plurality of flat plate-shaped portions that include a first end portion, a second end portion and an extending portion that extends in the first direction between the first end portion and the second end portion(Fig. 10, #1020, #1024, and #1030);
Feuerbaum does not disclose : at least two ridges protruding from at least two surfaces of at least two flat plate-shaped portions among the plurality of flat plate-shaped portions and extending along the first direction.
However, in the same field of endeavor, Boettcher teaches : at least two ridges protruding from at least two surfaces of at least two flat plate-shaped portions among the plurality of flat plate-shaped portions and extending along the first direction(Fig. 4a-4b, #426b and #426c may be in locations #218 and #214).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Boettcher to Feuerbaum to provide structural integrity to a wiring member (Boettcher [0014]).
Claim(s) 2-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feuerbaum et al, US 20220189855 in view of Boettcher et al, US 20190189545 in further view of Sunaga et al, US 20160181221.
Regarding claim 2, Feuerbaum as modified by Boettcher discloses : The semiconductor module according to claim 1.
Feuerbaum teaches : wherein: the first end portion joins the semiconductor chip(Fig. 10, #1030).
Feuerbaum as modified by Boettcher does not disclose : a first ridge among the at least two ridges is arranged on the extending portion.
However, in the same field of endeavor, Sunaga teaches : a first ridge among the at least two ridges is arranged on the extending portion(Fig. 11a, #36bl).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Sunaga to Feuerbaum and Boettcher to increase reliability of wiring member (Sunaga [0121-0122]).
Regarding claim 3, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 2.
Sonaga teaches : wherein: a second ridge among the at least two ridges is arranged on the extending portion(Fig. 11, #36b1 is on both ends).
Boettcher teaches : the extending portion includes: a first edge along the first direction(#426c); and a second edge along the first direction on an opposite side of the first edge in a width direction of the extending portion(#426b), the first ridge extends along the first edge(, and the second ridge extends along the second edge(#42b and #426c extending along wiring member #200).
Regarding claim 4, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 3.
Boettcher teaches : wherein: the extending portion includes: a first face adjacent to the substrate; and a second face opposite to the first face, and the first ridge and the second ridge protrude from the first face(Fig. 4c, #426b and #426c extending on a bottom surface of #218).
Regarding claim 5, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 2.
Boettcher teaches : wherein the one or more ridges include a third ridge among the at least two ridges is arranged on the first end portion(Fig. 4c, #218 to include #426b).
Regarding claim 6, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 5.
Boettcher teaches : wherein: a fourth ridge among the at least two ridges is arranged on the first end portion(Fig. 4c, #218 to include #426c), the first end portion includes: a third edge along the first direction(#426b along #218); and a fourth edge along the first direction on an opposite side of the third edge in a width direction of the first end portion(#426c along #218), the third ridge extends along the third edge, and the fourth ridge extends along the fourth edge(#426b and #426c may extend partially across #218 [0092]).
Regarding claim 7, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 6.
Boettcher teaches : wherein: the first end portion includes: a third face joined to the semiconductor chip; and a fourth face opposite to the third face, and the third ridge and the fourth ridge protrude from the third face(Fig. 4c, #426b and #426c extending on a bottom surface of #218).
Regarding claim 8, Feuerbaum as modified by Boettcher and Sunaga discloses : The semiconductor module according to claim 1.
Sunaga teaches : wherein heights of the at least two ridges are equal to or greater than widths of the at least two ridges(Fig. 11a, #3b1 shown to have a narrow width with a longer length [0121-0122]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE TAN whose telephone number is (571)272-6841. The examiner can normally be reached M-F: 8-4 PST.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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