Prosecution Insights
Last updated: May 04, 2026
Application No. 18/519,654

METHOD FOR MAKING A DEEP TRENCH ISOLATION BETWEEN HIGH VOLTAGE SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Nov 27, 2023
Examiner
NGUYEN, NIKI HOANG
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
833 granted / 919 resolved
+22.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
943
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
35.7%
-4.3% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 919 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/27/2023 has been considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 14-15, 18-21 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeda (US 20080020540 A1). Regarding claim 14, Takeda teaches a process for manufacturing in figs. 1-5, comprising: forming a first trench (501 in fig. 4A) in a first region (refer to right side region) of a first layer of material (300), the first trench (501) extending from an upper surface of the first layer of material (refer to an upper surface of 300); depositing a polymer layer (600; see par. 63) that partially closes a mouth of the first trench to provide an etch mask with an opening aligned with the first trench (501) (see fig. 4B); etching through the opening (503) in the etch mask formed by the polymer layer to extend the first trench to a deeper depth and form an extended first trench (see fig. 4B); removing the polymer layer (see fig. 5A; see par. 64); and filling the extended first trench with a conductive material (refer to aluminum film 217; see par. 65 and fig. 5B). Regarding claim 15, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches forming in a second region (refer to left side region) of the first layer of material (300) an element (refer to an MIM capacitor) indistinct from the trench (501); wherein the deposited polymer layer (600) at least partially covers the element (see par. 63; fig. 4B). Regarding claim 18, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches forming in a second region of the first layer of material (refer to the left side region of 300) a second trench (refer to 500 in fig. 4A) extending from an upper surface of the first layer of material (refer to the upper surface of 300); wherein said first trench (501) has a first width and said second trench (500) has a second width, where said second width is larger than the first width (see fig. 4A); wherein said polymer layer (600) partially closes a mouth of the second trench (500) (see fig. 4B); etching to extend the second trench to a deeper depth (see fig. 4B); and wherein filling further comprises filling the second trench with the conductive material (refer to 217 in fig. 5B). Regarding claim 19, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches conductive material (217) filling the extended first and second trenches forms an electrical contact (see fig. 5B). Regarding claim 20, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches the extended first trench (501) includes an upper portion (refer to trench width of trench 501) and a lower portion (refer to a width portion of trench 503), and wherein the lower portion has a taper which narrows in width from a width of the upper portion (see figs. 4-5). Regarding claim 21, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches conductive material (217) filling the extended first trench (501/503) forms an electrical contact (see fig. 5B). Regarding claim 24, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Takeda teaches said deeper depth is substantially equal to a thickness of the first layer of material so that the extended first trench reaches a second layer of material (100) under said first layer of material (see par. 62). NOTE: Fig. 4B shows the opening 503 us extending from the upper surface of 300 to touch the metal interconnect 701 which reaching to the second material 100. whose thickness is defined as 100nm. Since the thickness of interconnect 701 is defined as 100nm is be relatively small, the depth of the opening 503 is considered to be substantially equal to the thickness of the material layer 300. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Takeda as applied to claim 14 above, and further in view of Brand (CN 101128528B) Regarding claim 22, Takeda teaches all the limitations of the claimed invention for the same reasons as set forth above except for the polymer layer comprises a halogen-based polymer. Brand teaches the same field of an endeavor wherein the polymer layer comprises a halogen-based polymer (see par. 46). Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the polymer layer comprises a halogen-based polymer as taught by Brand in the teaching of Takeda in order to provide oil resistance and water resistance (see par. 2). Regarding claim 23, Takeda and Brand teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Brand teaches the halogen is Fluorine (see par. 46). Allowable Subject Matter Claims 1-13 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a process for manufacturing a semiconductor device, comprising: “depositing a polymer layer that closes the residual opening in the second trench and leaves partially open the residual opening in the first trench to provide an etch mask with an opening over first trench; etching through the opening in the etch mask formed by the polymer layer to remove the insulation liner at the bottom of the first trench and expose the semiconductor material body; removing the polymer layer from the first trench and second trench; and filling the residual openings in the first trench and second trench with a conductive material to form a substrate plug in the first trench that is in contact with the semiconductor material body at the bottom of the first trench and form a field plate electrode in the second trench that is isolated from the semiconductor material body by the insulation liner in the second trench” in combination of all of the limitations of claim 1. Claims 2-7 include all of the limitations of claim 1. Regarding claim 8, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a process for manufacturing a semiconductor device, comprising: “depositing a halogen-based polymer material that covers at least an upper portion of the insulation material in the first trench and leaves free a portion of the insulation material at the bottom of the first trench and further covers the insulation material at the sidewalls and bottom of the second trench; d) subsequent to step c), removing the portion of the insulation material at the bottom of the first trench; and e) subsequent to step d), removing the halogen-based polymer material from the first trench and second trench” in combination of all of the limitations of claim 8. Claims 9-13 include all of the limitations of claim 8. Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “said element includes an oxide layer, and wherein said deposited polymer layer completely covers the oxide layer” . Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “said element is a capacitor including a capacitor dielectric layer, and wherein said deposited polymer layer completely covers the capacitor dielectric layer”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Nov 27, 2023
Application Filed
Apr 03, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+5.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 919 resolved cases by this examiner. Grant probability derived from career allowance rate.

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