DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 01/02/2026 Amendment.
Claims 1-16 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,631,687 to Suzuki et al. (hereafter Suzuki).
Regarding independent claim 1, Suzuki teaches a memory device comprising:
a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated (FIG. 36: memory array MA1 between hookup area HA1 and contact area CA in the X direction);
a word line connected to a memory cell located in the cell region (FIG. 35: e.g. word line WL11 in MA1);
a first drain selection line connected to a first drain selection transistor positioned over the memory cell in the cell region (FIG. 35: e.g. SGD line 24a);
a first drain contact connected to the first drain selection line in the first connection region (FIG. 35: contact SCa, also see Annotated FIG. 36 below);
a second drain contact connected to the first drain selection line in the second connection region (see annotated FIG. 36 below); and
a first drain voltage supply line connected to the first and second drain contacts (FIG. 36: shunt line SHT0, see 24:44-59).
Annotated FIG. 36
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Regarding dependent claim 2, Suzuki teaches a peripheral circuit positioned under the memory block (FIG. 13: insulating layer 40, see 14:38-42).
Regarding dependent claim 3, Suzuki teaches a cell plug positioned between a bit line and a source line in the cell region of the memory block (FIG. 35: memory pillar MP).
Regarding dependent claim 4, Suzuki teaches wherein the cell plug comprises: a first drain selection transistor contacting the first drain selection line (FIG. 2: transistor ST1); and a memory cell contacting the word line (FIG. 2: memory cell MT11 contacting WL11).
Regarding dependent claim 5, Suzuki implicitly teaches wherein the bit line is positioned between the first drain voltage supply line and the first drain selection line (FIG. 35: bit line 25 is at the same level as the conductive layer 27 coupled to SGD line 24a. It is seen that the shunt line SHT0 should be above bit line 25).
Regarding dependent claim 6, Suzuki implicitly teaches wherein the first drain selection transistor is configured to be turned on or turned off in response to a voltage applied from the first and second connection regions of the first drain selection line (because first and second connection regions of transistor ST1 are coupled to the same shunt line SHT0).
Regarding dependent claim 7, Suzuki teaches a second drain selection line (FIG. 35: e.g. SGD line 24b) connected to a second drain selection transistor over the first drain selection transistor (FIG. 35: not-shown SGD transistor coupled to conductive layer 24b); a third drain contact connected to the second drain selection line in the first connection region; a fourth drain contact connected to the second drain selection line in the second connection region (see annotated FIG. 36 above); and a second drain voltage supply line connected to the third and fourth drain contacts (FIG. 36: shunt line SHT1, see 24:44-59).
Regarding dependent claim 8, Suzuki teaches wherein in the first and second connection regions, the first and second drain selection lines have a step structure in which upper surfaces are exposed, respectively (FIG. 35: step structure for SGD as shown).
Regarding dependent claim 9, Suzuki teaches wherein the first and second drain contacts are spaced apart from the second drain selection line (see annotated FIG. 36 above).
Regarding dependent claim 10, Suzuki teaches wherein in the first and second connection regions, only an upper surface of the second drain selection line of the first and second drain selection lines is exposed (FIG. 35: step structure for SGD with supper surface expose as shown).
Regarding dependent claim 13, Suzuki teaches a third drain selection line connected to a third drain selection transistor positioned on the same layer as the first drain selection line; a drain separation pattern electrically separating between the first and third drain selection lines; a fifth drain contact connected to the third drain selection line in the first connection region; a sixth drain contact connected to the third drain selection line in the second connection region; and a third drain voltage supply line connected to the fifth and sixth drain contacts (see Annotated FIG. 36 above, wherein the third drain selection line is the SGD0a of second block BLK1).
Regarding dependent claim 11, Suzuki teaches wherein the second drain selection line includes holes through which the first and second drain contacts pass (FIG. 26: when all SGD 24 share the same contact SC as shown).
Regarding dependent claim 12, Suzuki implicitly teaches wherein in the holes, the first and second drain contacts are spaced apart from inner walls of the holes (in order to avoid short circuit).
Regarding independent claim 14, Suzuki teaches a memory device comprising:
first and second connection regions and a cell region between the first and second connection regions (FIG. 3: memory array MA1 between hookup area HA1 and contact area CA in the X direction);
a first drain selection line extended in a first direction to be located within the first and second connection regions and the cell region (1st SDG line, which is closest to WL11 in FIG. 8 or SGD0a in FIG. 9 in X direction);
a bit line extended in a second direction perpendicular to the first direction and positioned on the first drain selection line in the cell region (FIG. 5: BL in Y direction);
a first drain contact connected to the first drain selection line in the first connection region (FIG. 8: not-shown contact between 1st SDG line and SC in hookup area HA1);
a second drain contact connected to the first drain selection line in the second connection region (FIG. 9: contact SC0a in contact area CA);
a first drain voltage supply lineFIG. 8: conductive layer 27 on hookup area HA1); and
a second drain voltage supply lineFIG. 9: interconnect SW0 in contact area CA), wherein the first and second drain voltage supply lines and the bit line are positioned on the same plane (FIG. 8: conductive layer 27 and BL 25 are position on the same plane as shown. There appears interconnect SW0 should be on the same layer as conductive layer 27 because they serve similar purpose for drain selection line).
Regarding dependent claim 15, Suzuki teaches a second drain selection line positioned between the first drain selection line and the bit line (2nd SDG line, which is middle of the three in FIG. 8 or SGD1a of FIG. 9); a third drain contact connected to the second drain selection line in the first connection region (FIG. 8: not-shown contact between 2nd SDG line and SC in hookup area HA1); a fourth drain contact connected to the second drain selection line in the second connection region (FIG. 9: contact SC1a in contact area CA); a third drain voltage supply line connected to the third drain contact (FIG. 8: conductive layer 27 on hookup area HA1); and a fourth drain voltage supply line connected to the fourth drain contact (FIG. 9: interconnect SW1 in contact area CA), wherein the first to fourth drain voltage supply lines and the bit line are disposed on the same plane (FIG. 8: conductive layer 27 and BL 25 are position on the same plane as shown. There appears interconnect SW01 should be on the same layer as conductive layer 27 because they serve similar purpose for drain selection line).
Regarding independent claim 16, Suzuki teaches a memory device comprising:
a voltage generator configured to output a drain voltage through a global line (FIG. 1: driver module 14 for generating voltages that is to be used for the memory cell array 10, see 11:14:30);
a row decoder connected to the voltage generator through the global line and transferring the drain voltage to a drain voltage supply line (FIG. 1: row decoder 15, see 11:14:30);
a drain selection line connected to a drain selection transistor in a memory block, wherein the drain selection transistor located between a bit line and a memory cell (FIGS. 2 and 8: drain selection transistor ST1); and
drain contacts connected to both ends of the drain selection line, wherein the drain selection transistor is located in a region between the drain contacts, wherein the drain contacts are connected to the drain voltage supply line (see annotated FIG. 36 above).
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 19, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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