DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2018/0151114).
Regarding claim 1, Choi et al. discloses, as shown in Figures 5-11B, a thin-film transistor substrate comprising:
a first oxide semiconductor film (119, [0068]);
a second oxide semiconductor film (129, [0075]) located upper than the first oxide semiconductor film;
a first insulating film (103, [0065]) located lower than the second oxide semiconductor film and covering the first oxide semiconductor film; and
a gate electrode (114, [0065]) of a first thin-film transistor (Tsw1, [0068]),
wherein the first oxide semiconductor film includes a first low-resistive region (111, conductor part is low resistive region, [0068]), a second low-resistive region (112, conductor part is low resistive region, [0068]), and a channel region (113 part of 119, [0068]) of the first thin-film transistor that is located between the first low-resistive region and the second low-resistive region and opposed to the gate electrode,
wherein each of the first low-resistive region and the second low-resistive region includes a source/drain region of the first thin-film transistor [0070],
wherein the second oxide semiconductor film includes a third low-resistive region (121, conductor part is low resistive region, [0075]), a fourth low-resistive region (122, conductor part is low resistive region, [0075]), and a channel region (123 part of 129, [0075]) of a second thin-film transistor (Tdr, [0070]) that is located between the third low-resistive region and the fourth low-resistive region,
wherein each of the third low-resistive region and the fourth low-resistive region includes a source/drain region of the second thin-film transistor [0075], and
wherein a part of the first low-resistive region (111) extending from a source/drain region of the first thin-film transistor is a bottom-gate electrode of the second thin-film transistor opposed to the channel region of the second thin-film transistor [0070].
Regarding claim 5, Choi et al. discloses the first thin-film transistor is a switching transistor, and wherein the second thin-film transistor is a transistor configured to adjust an amount of electric current in a channel region in accordance with a control signal [0049].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2018/0151114) in view of Kim et al. (US 2015/0123084).
Regarding claim 2, Choi et al. discloses the claimed invention including the thin-film transistor substrate as explained in the above rejection. Choi et al. further discloses the thin-film transistor substrate further comprising:
a second insulating film (104) located upper than the first insulating film (103),
wherein the gate electrode (114) of the first thin-film transistor is a top-gate electrode, wherein the second insulating film (104) covers the top-gate electrode,
wherein a part of the first insulating film (103) is located between the top-gate electrode and the channel region (113) of the first thin-film transistor, and
wherein a part of the second insulating film (104) is located between the bottom-gate electrode (111) and the channel region (123) of the second thin-film transistor.
Choi et al. does not disclose another part of the first insulating film is located between the bottom-gate electrode and the channel region of the second thin-film transistor. However, Kim et al. discloses a part (portion of 113 between 222c and 224) of a first insulating film (113) is located between a top-gate electrode (224) and a channel region (222c) of a first thin-film transistor (22) and another part (portion of 113 between 212c and 215) is located between a bottom-gate electrode (212) and a channel region (215) of a second thin-film transistor (21). Note Figures 4-7 of Kim et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the first insulating film of Choi et al. having another part of the first insulating film is located between the bottom-gate electrode and the channel region of the second thin-film transistor, such as taught by Kim et al. in order to have the desired structure.
Regarding claim 3, Choi et al. and Kim et al. disclose another part of the first low-resistive region (111) extending from the source/drain region of the first thin-film transistor is opposed to a part of the third low-resistive region (121) with a multilayer insulating film including the first insulating film and the second insulating film interposed therebetween to configure a first capacitive element (part of Cst2) [Figure 5].
Regarding claim 8, Choi et al. discloses the claimed invention including the thin-film transistor substrate as explained in the above rejection. Choi et al. does not disclose a top-gate electrode of the second thin-film transistor. However, Kim et al. discloses a top-gate electrode (217) of a second thin-film transistor (21). Note Figures 4-7 of Kim et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the thin-film transistor substrate of Choi et al. having a top-gate electrode of the second thin-film transistor, such as taught by Kim et al. in order to have the desired configuration.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2018/0151114) in view of Hayashi (US 2017/0309649).
Regarding claim 6, Choi et al. discloses the claimed invention including the thin-film transistor substrate as explained in the above rejection. Choi et al. does not disclose the channel region of the second thin-film transistor has lower mobility than the channel region of the first thin-film transistor. However, Hayashi discloses a thin-film transistor substrate having a channel region of a second thin-film transistor (2) has lower mobility than a channel region of a first thin-film transistor (1). Note Figure 2A, [0060], and [0091] of Hayashi. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the thin-film transistor substrate of Choi et al. comprising the channel region of the second thin-film transistor having lower mobility than the channel region of the first thin-film transistor, such as taught by Hayashi in order to have the desired speed of the device.
Regarding claim 7, Choi et al. discloses the claimed invention including the thin-film transistor substrate as explained in the above rejection. Choi et al. does not disclose the first oxide semiconductor film and the second oxide semiconductor film are different in material or composition distribution. However, Hayashi discloses a thin-film transistor substrate having the first oxide semiconductor film (41) and the second oxide semiconductor film (42) are different in material or composition distribution. Note Figures 2A-2B, and [0091]-[0091] of Hayashi. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the thin-film transistor substrate of Choi et al having the first oxide semiconductor film and the second oxide semiconductor film are different in material or composition distribution, such as taught by Hayashi in order to have the desired mobility.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2018/0151114) in view of Yamanaka et al. (US 2022/0005838).
Choi et al. discloses the claimed invention including the thin-film transistor substrate as explained in the above rejection. Choi et al. does not disclose the channel region of the first thin-film transistor has a larger width than the channel region of the second thin-film transistor. However, Yamanaka et al. discloses a thin-film transistor substrate comprising a channel region of a first thin-film transistor (100) has a width different than a channel region of a second thin-film transistor (200). Note Figure 2 and [0142] of Yamanaka et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the thin-film transistor substrate of Choi et al. having the channel region of the first thin-film transistor has a larger width than the channel region of the second thin-film transistor, such as taught by Yamanaka et al. in order to have the desired mobility.
Further, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant's claim 4 is allowable over the references of record because none of these references disclose or can be combined to yield the claimed conductor film including a top-gate electrode of the second thin-film transistor, wherein the conductor film is connected to the third low-resistive region, and wherein a part of the first low-resistive region is opposed to a part of the conductor film with an insulating film interposed therebetween to configure a second capacitive element in parallel to the first capacitive element, as recited in claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG K VU/ Primary Examiner, Art Unit 2897