DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (U.S. PGPub 2019/0288048).
Regarding claim 1, Kang teaches a thin-film transistor substrate (Fig. 2) comprising: a first insulating film (111, [0057]), a second insulating film located upper than the first insulating film (113, [0063]), a first thin-film transistor, a second thin-film transistor, a capacitive element (T1, T2, Cst, [0047]), wherein the first thin-film transistor includes a top-gate electrode and a first semiconductor region located above the first insulating film (G1, AS1, [0048]), wherein the second thin-film transistor includes a second semiconductor region located above the second insulating film (AO2, [0049]), wherein the capacitive element includes at least a part of the top-gate electrode and a first low-resistive semiconductor region of the same semiconductor layer that includes the second semiconductor region, the first low-resistive semiconductor region overlapping at least a part of the top-gate electrode with an insulating film interposed therebetween (C1/G1, C2, [0063], [0068]).
Regarding claim 2, Kang teaches wherein the second semiconductor region and the first low-resistive semiconductor region are made of an oxide semiconductor ([0068]).
Regarding claim 4, Kang teaches wherein the first semiconductor region is made of polysilicon, and wherein the second semiconductor region and the first low-resistive semiconductor region are made of an oxide semiconductor ([0060], [0068]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Jeong (U.S. PGPub 2019/0355799).
Regarding claim 3, Kang does not explicitly teach wherein the first semiconductor region is made of an oxide semiconductor. Kang teaches wherein the first semiconductor region is a polysilicon region ([0060]).
Jeong teaches a first tft and a second tft, where the semiconductor region of the first tft may be polysilicon or an oxide semiconductor layer and the semiconductor region of the second tft is an oxide semiconductor layer (Fig. 4, TR1, TR2, 120, 150, [0037], [0046]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Jeong with Kang such that the first semiconductor region is made of an oxide semiconductor. Kang teaches wherein the first semiconductor region is a polysilicon region because the prior art teaches an element which differs from the claim by substitution with a different element, the claimed element is known in the art, a person of ordinary skill could have substituted one known element for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Murai (U.S. PGPub 2018/0158848).
Regarding claims 5-6, Kang teaches wherein a second low-resistive semiconductor region that adjoins a channel region in the first semiconductor region and a third low-resistive semiconductor region that adjoins a channel region in the second semiconductor region are connected (Fig. 18, [0173], source electrode of T1 is connected to drain electrode of T2) but does not explicitly teach where the regions are connected via a contact region, wherein the contact region is included in the third low-resistive semiconductor region, and wherein the contact region extends through the second insulating film and is directly connected to the second low-resistive semiconductor region.
Murai teaches wherein a source/drain region of a first transistor and a source/drain region of a second transistor are connected via a contact region, wherein the contact region is included in the source/drain region of the second transistor, and wherein the contact region extends through an insulating film formed over the first transistor and is directly connected to the source/drain region of the first transistor (Figs. 13-14, 13b/17b, 19B/22D/22A, 16, [0085], [0095]-[0096]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Murai with Kang such that the regions are connected via a contact region, wherein the contact region is included in the third low-resistive semiconductor region, and wherein the contact region extends through the second insulating film and is directly connected to the second low-resistive semiconductor region for the purpose of implementing the connection as taught by Kang in Fig. 18.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Tan (U.S. PGPub 2016/0300532).
Regarding claims 7-8, Kang does not explicitly teach wherein the top-gate electrode of the first thin-film transistor is connected to a fourth low-resistive semiconductor region that adjoins a channel region in the second semiconductor region, wherein the first low-resistive semiconductor region further includes a contact region, and wherein the contact region extends through the second insulating film and is directly connected to a fifth low-resistive semiconductor region that adjoins a channel region in the first semiconductor region.
Tan teaches a TFT substrate having a first TFT, a second TFT, and a capacitive element, where a top gate of the first TFT is directly connected to a source/drain region of the second TFT and wherein a first electrode of the capacitor is directly connected to the source/drain of the first TFT (Fig. 3, DTFT, TC, Cs, [0073], [0075]-[0076], [0082]; compare with application Fig. 3).
Examiner takes official notice that direct connections between TFT elements are made through contact regions between the elements.
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Tan with Kang such that the device comprises the top-gate electrode of the first thin-film transistor is connected to a fourth low-resistive semiconductor region that adjoins a channel region in the second semiconductor region, wherein the first low-resistive semiconductor region further includes a contact region, and wherein the contact region extends through the second insulating film and is directly connected to a fifth low-resistive semiconductor region that adjoins a channel region in the first semiconductor region for the purpose of providing the improved integration density and decreased process time and cost of Kang ([0054]) for the pixel circuit of Tan ([0039]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Murai (U.S. PGPub 2018/0158848) and Zhao (U.S. PGPub 2018/0108746).
Regarding claim 9, Kang and Murai do not explicitly teach wherein a part of the second low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region.
Zhao teaches wherein a part of a TFT source/drain region in contact with a contact region has a higher impurity concentration than a part outside the part in contact with the contact region (Fig. 14, 150a/b, 190a/b, [0029]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhao with Kang and Murai such that a part of the second low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region for the purpose of decreasing the contact resistance (Zhao, [0029]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 20190288048) in view of Tan (U.S. PGPub 2016/0300532) and Zhao (U.S. PGPub 2018/0108746).
Regarding claim 10, Kang and Tan do not explicitly teach wherein a part of the fifth low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region.
Zhao teaches wherein a part of a TFT source/drain region in contact with a contact region has a higher impurity concentration than a part outside the part in contact with the contact region (Fig. 14, 150a/b, 190a/b, [0029]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhao with Kang and Tan such that a part of the fifth low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region for the purpose of decreasing the contact resistance (Zhao, [0029]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 20190288048) in view of Koezuka (U.S. PGPub 2016/0322395).
Regarding claim 11, Kang teaches wherein the first low-resistive semiconductor region is made conductive during the same process as the source/drain regions of the second tft (Figs. 6-7, [0099]) but does not explicitly teach wherein the first low-resistive semiconductor region contains at least one element selected from helium, argon, hydrogen, boron, and phosphorus.
Koezuka teaches wherein regions of an oxide semiconductor film is made conductive by adding an impurity which may be helium, argon, hydrogen, boron, or phosphorus ([0119]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Koezuka with Kang such that the first low-resistive semiconductor region contains at least one element selected from helium, argon, hydrogen, boron, and phosphorus because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination as taught by [References] would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812