DETAILED ACTION
Response to Arguments
Applicant's arguments filed 5/04/26 have been fully considered but they are not persuasive.
Regarding claim 1, new art was used to reject amended independent claim 1, rendering the arguments moot.
Regarding claim 7, Applicant has amended in the limitations of previous dependent claims 8 and 10. Applicant argues that the reference Tan does not teach all of the limitations of amended claim 7 (Remarks, p. 11-13). Applicant has not addressed or traversed the finding of official notice (see MPEP 2144.03) or the teachings of Zhao, which was used to reject the limitations of previous dependent claim 10. The rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Ono (U.S. PGPub 2018/0277614).
Regarding claim 1, Kang teaches a thin-film transistor substrate (Fig. 2) comprising:
a first insulating film (111, [0057]),
a second insulating film located upper than the first insulating film (113, [0063]),
a first thin-film transistor including a top-gate electrode and a first semiconductor region located above the first insulating film (T1, G1, AS1, [0047]-[0048]),
a second thin-film transistor including a second semiconductor region located above the second insulating film (T2, [0047], AO2, [0049]),
a capacitive element including at least a part of the top-gate electrode and a first low-resistive semiconductor region of the same semiconductor layer that includes the second semiconductor region, the first low-resistive semiconductor region overlapping at least a part of the top-gate electrode with an insulating film interposed therebetween (C1/G1, C2, [0063], [0068]),
wherein a second low-resistive semiconductor region that adjoins a channel region in the first semiconductor region and a third low-resistive semiconductor region that adjoins a channel region in the second semiconductor region are connected (Fig. 18, [0173], source electrode of T1 is connected to drain electrode of T2) but does not explicitly teach wherein the second low-resistive semiconductor region and the third low-resistive semiconductor region are connected via two or fewer contact regions.
Huang teaches wherein a source/drain region of a first transistor and a source/drain region of a second transistor are connected via two or fewer contact regions (Fig. 8, CNT1/CNT2, [0072]-[0076]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Ono with Kang such that the second low-resistive semiconductor region and the third low-resistive semiconductor region are connected via two or fewer contact regions for the purpose of implementing the connection as taught by Kang in Fig. 18 and reducing the number of masks and contact holes (Ono, [0072]).
Regarding claim 2, the combination of Kang and Ono teaches wherein the second semiconductor region and the first low-resistive semiconductor region are made of an oxide semiconductor (Kang, [0068]). It would have been obvious to a person of ordinary skill in the art to further combine the teachings of Kang and Ono for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Kang and Ono teaches wherein the first semiconductor region is made of polysilicon, and wherein the second semiconductor region and the first low-resistive semiconductor region are made of an oxide semiconductor (Kang, [0060], [0068]). It would have been obvious to a person of ordinary skill in the art to further combine the teachings of Kang and Ono for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Kang and Ono teaches wherein at least one of the two or fewer contact regions is included in the third low-resistive semiconductor region and wherein the at least one contact region extends through the second insulating film and is directly connected to the second low-resistive semiconductor region (Ono, Fig. 8, 800, [0074]-[0075]). It would have been obvious to a person of ordinary skill in the art to further combine the teachings of Kang and Ono for the reasons set forth in the rejection of claim 1.
Regarding claim 11, the combination of Kang and Ono teaches wherein the first low-resistive semiconductor region contains hydrogen (Figs. 6-7, [0099]-[0100]). It would have been obvious to a person of ordinary skill in the art to further combine the teachings of Kang and Ono for the reasons set forth in the rejection of claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Ono (U.S. PGPub 2018/0277614) and Jeong (U.S. PGPub 2019/0355799).
Regarding claim 3, Kang does not explicitly teach wherein the first semiconductor region is made of an oxide semiconductor. Kang teaches wherein the first semiconductor region is a polysilicon region ([0060]).
Jeong teaches a first tft and a second tft, where the semiconductor region of the first tft may be polysilicon or an oxide semiconductor layer and the semiconductor region of the second tft is an oxide semiconductor layer (Fig. 4, TR1, TR2, 120, 150, [0037], [0046]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Jeong with Kang such that the first semiconductor region is made of an oxide semiconductor because the prior art teaches an element which differs from the claim by substitution with a different element, the claimed element is known in the art, a person of ordinary skill could have substituted one known element for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Tan (U.S. PGPub 2016/0300532) and Zhao (U.S. PGPub 2018/0108746).
Regarding claim 7, Kang teaches a thin-film transistor substrate (Fig. 2) comprising:
a first insulating film (111, [0057]),
a second insulating film located upper than the first insulating film (113, [0063]),
a first thin-film transistor including a top-gate electrode and a first semiconductor region located above the first insulating film (T1, G1, AS1, [0047]-[0048]),
a second thin-film transistor including a second semiconductor region located above the second insulating film (T2, [0047], AO2, [0049]),
a capacitive element including at least a part of the top-gate electrode and a first low-resistive semiconductor region of the same semiconductor layer that includes the second semiconductor region, the first low-resistive semiconductor region overlapping at least a part of the top-gate electrode with an insulating film interposed therebetween (C1/G1, C2, [0063], [0068]),
Kang does not explicitly teach wherein the top-gate electrode of the first thin-film transistor is connected to a second low-resistive semiconductor region that adjoins a channel region in the second semiconductor region, wherein the first low-resistive semiconductor region further includes a contact region extending through the second insulating film and directly connected to a third low-resistive semiconductor region that adjoins a channel region in the first semiconductor region.
Kang teaches wherein the second insulating film is between the first low-resistive semiconductor region and a third low-resistive semiconductor region that adjoins a channel region in the first semiconductor region (Fig. 2, C2, 113, S1).
Tan teaches a TFT substrate having a first TFT, a second TFT, and a capacitive element, where a top gate of the first TFT is directly connected to a source/drain region of the second TFT and wherein a first electrode of the capacitor is directly connected to the source/drain of the first TFT (Fig. 3, DTFT, TC, Cs, [0073], [0075]-[0076], [0082]; compare with application Fig. 3).
Examiner takes official notice that direct connections between TFT elements are made through contact regions between the elements.
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Tan with Kang such that the top-gate electrode of the first thin-film transistor is connected to a second low-resistive semiconductor region that adjoins a channel region in the second semiconductor region, wherein the first low-resistive semiconductor region further includes a contact region extending through the second insulating film and directly connected to a third low-resistive semiconductor region that adjoins a channel region in the first semiconductor region for the purpose of providing the improved integration density and decreased process time and cost of Kang ([0054]) for the pixel circuit of Tan ([0039]).
Kang does not explicitly teach wherein a part of the third low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region.
Zhao teaches wherein a part of a TFT source/drain region in contact with a contact region has a higher impurity concentration than a part outside the part in contact with the contact region (Fig. 14, 150a/b, 190a/b, [0029]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhao with Kang and Tan such that a part of the third low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region for the purpose of decreasing the contact resistance (Zhao, [0029]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Ono (U.S. PGPub 2018/0277614) and Zhao (U.S. PGPub 2018/0108746).
Regarding claim 9, Kang and Ono do not explicitly teach wherein a part of the second low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region.
Zhao teaches wherein a part of a TFT source/drain region in contact with a contact region has a higher impurity concentration than a part outside the part in contact with the contact region (Fig. 14, 150a/b, 190a/b, [0029]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhao with Kang and Ono such that a part of the second low-resistive semiconductor region in contact with the contact region has a higher impurity concentration than a part outside the part in contact with the contact region for the purpose of decreasing the contact resistance (Zhao, [0029]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PGPub 2019/0288048) in view of Ono (U.S. PGPub 2018/0277614) and Kim (U.S. PGPub 2019/0189723).
Regarding claim 9, the combination of Kang and Ono does not explicitly teach wherein the first low-resistive semiconductor region further includes a contact region, and wherein the contact region extends through the second insulating film and is directly connected to another low-resistive semiconductor region that adjoins a channel region in the first semiconductor region.
Kang teaches wherein the source/drain contacts may be low-resistive semiconductor regions ([0076]) and wherein the second insulating film is between the first low-resistive semiconductor region and the source/drain regions of the same transistor (Fig. 2, 113).
Kim teaches a capacitive element including a low-resistive semiconductor region and a gate electrode, wherein the low-resistive semiconductor region further includes a contact region, and wherein the contact region is directly connected to another low-resistive semiconductor region that adjoins a channel region in the first semiconductor region (Fig. 7, 102, 106/110S, Cst, [0058]-[0060]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Kang and Ono such that the first low-resistive semiconductor region further includes a contact region, and wherein the contact region extends through the second insulating film and is directly connected to another low-resistive semiconductor region that adjoins a channel region in the first semiconductor region for the purpose of reducing complexity of the device and because
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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