DETAILED ACTION
This Notice is responsive to communication filed on 11/27/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/11/2024 and 11/27/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "one of the second semiconductor chips, which is provided on the lowermost second semiconductor chip..." in lines 11-12. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the present Office Action, the limitation will be interpreted as “a lowermost second semiconductor chip” of the second semiconductor chips.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 20230413585).
Regarding claim 1, Choi teaches a semiconductor device comprising:
a substrate Fig. 16: 110 having a first surface Fig. 16: 112;
a first spacer Fig. 16: 300 and a second spacer Fig. 16: 300 that are provided at different positions on the first surface Fig. 16: 112;
a first semiconductor chip Fig. 16: 200 provided on the first surface Fig. 16: 112 so as to be disposed between the first spacer Fig. 16: 300 and the second spacer Fig. 16: 300; and
a stacked body Fig. 16: G1, G2, G3, G4 that is provided above the first spacer Fig. 16: 300, the second spacer Fig. 16: 300, and the first semiconductor chip Fig. 16: 200 and in which a plurality of second semiconductor chips Fig. 16: 400, 500, 600, 700 are stacked in a first direction substantially perpendicular to the first surface (shown in Fig. 16),
wherein one of the second semiconductor chips Fig. 16: 400b, which is provided on the lowermost second semiconductor chip Fig. 16: 400a, is stacked with an offset relative to the lowermost second semiconductor chip Fig. 16: 400a in a second direction substantially parallel to the first surface Fig. 16: 112 (right direction of Fig. 16), and
a central position of the first semiconductor chip Fig. 16: 200 is separated from a central position of the lowermost second semiconductor chip Fig. 16: 400a in the second direction when viewed in the first direction (when viewed in a direction from the top of the device, there is an offset in the direction towards the right of the device).
Regarding claim 2, Choi teaches the semiconductor device according to claim 1, wherein the central position of the first semiconductor chip Fig. 16: 200 is separated from the central position of the lowermost second semiconductor chip Fig. 16: 400a in the second direction by 1/2 or more of an offset amount of the second semiconductor chip Fig. 16: 400b on the lowermost second semiconductor chip Fig. 16: 400a.
Regarding claim 3, Choi teaches the semiconductor device according to claim 1, wherein an offset amount between each two of the second semiconductor chips Fig. 16: 400, 500, 600, 700 in the second direction is different for each of the second semiconductor chips, the two second semiconductor chips being stacked adjacent to each other (i.e. between 400a and 400b).
Regarding claim 4, Choi teaches the semiconductor device according to claim 1, wherein the stacked body Fig. 16: G1, G2, G3, G4 includes four of the second semiconductor chips Fig. 16: 400a-d, the four second semiconductor chips Fig. 16: 400a-d being continuously stacked with offsets in the second direction (offset towards the right of the device).
Regarding claim 5, Choi teaches the semiconductor device according to claim 4, wherein the stacked body Fig. 16: G1, G2, G3, G4 includes at least one first chip group Fig. 16: G1 including four of the second semiconductor chips Fig. 16: 400a-d, the four second semiconductor chips Fig. 16: 400a-d being continuously stacked with offsets in the second direction, and at least one second chip group Fig. 16: G2 including four of the second semiconductor chips Fig. 16: 500a-d, the second semiconductor chips Fig. 16: 500a-d being continuously stacked with offsets in a direction opposite the second direction, and the first Fig. 16: G1 and second Fig. 16: G2 chip groups are alternately stacked (shown in Fig. 16).
Regarding claim 6, Choi teaches the semiconductor device according to claim 4, wherein the three upper second semiconductor chips Fig. 16: 400b-d among the four second semiconductor chips Fig. 16: 400a-d continuously stacked with offsets in the second direction each have a thickness of 20 μm or larger and 100 μm or smaller (para. 0040 teaches a range that falls within the range of the claimed invention; i.e. 15-40 µm).
Regarding claim 7, Choi teaches the semiconductor device according to claim 1, wherein the lowermost second semiconductor chip Fig. 16: 400a has a thickness of 40 μm or larger and 200 μm or smaller (para. 0039 teaches a range that includes the range of the claimed invention; i.e. 40-400 µm).
Regarding claim 11, Choi teaches the semiconductor device according to claim 1, further comprising a dummy chip provided on the first spacer Fig. 16: 300, the second spacer Fig. 16: 300, and the first semiconductor chip Fig. 16: 200, wherein the stacked body Fig. 16: G1, G2, G3, G4 is provided on the dummy chip (para. 0095 teaches each spacer may include a dummy substrate or a dummy chip).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20230413585) as applied to claim 1 above, and further in view of Kyung et al. (US 20220149010).
Regarding claim 8, although Choi teaches the substantial features of the present invention, including the semiconductor device according to claim 1, wherein the first semiconductor chip has a substantially rectangular shape when viewed in the first direction, Choi does not explicitly teach the second direction is a short side direction of the first semiconductor chip. However, Kyung discloses wherein the first semiconductor chip Fig. 1: 200 has a substantially rectangular shape when viewed in the first direction, and the second direction is a short side direction of the first semiconductor chip Fig. 1: 200 (shown in Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Choi and Kyung, following the standard practice in the art of having a chip that maintains a rectangular shape (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)).
Regarding claim 9, Choi fails to explicitly teach the semiconductor device according to claim 1, wherein the first spacer and the second spacer are disposed side by side in a third direction substantially perpendicular to both the first direction and the second direction. However, Kyung teaches wherein the first spacer Fig. 1: 300-1 and the second spacer Fig. 1: 300-2 are disposed side by side in a third direction (D1) substantially perpendicular to both the first direction (D2) and the second direction (an upward direction). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Choi and Kyung’s teachings for the purpose of defining a perimeter around the semiconductor chip to attain uniform distribution of a weight of the chip stack, and protecting the semiconductor chip from external impact (para. 0034).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20230413585) as applied to claim 1 above, and further in view of Park et al. (US 20220077114).
Regarding claim 10, Choi doesn’t explicitly show the semiconductor device according to claim 1, wherein no spacers are provided beside the first semiconductor chip in the second direction. However, Park shows in Fig. 9, wherein no spacers Fig. 9: 730 are provided beside the first semiconductor chip Fig. 9: 710 in the second direction (annotated below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Choi and Park for the purpose of increasing the number of passive devices that can be disposed in the stack package, improving the electrical characteristics of the stack package.
Conclusion
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 29, 2026