DETAILED ACTION
This Notice is responsive to communication filed on 04/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1-12, and 14-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "one of the second semiconductor chips, which is provided on " in lines 11-12. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the present Office Action, the limitation will be interpreted as “a lowermost second semiconductor chip” of the second semiconductor chips.
Claim 6 recites the limitation “wherein the three upper second semiconductor chips…” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the present Office Action, the limitation will be interpreted as “wherein three upper second semiconductor chips…” among the four second semiconductor chips.
Claim 12 recites the limitation “the first layer” in lines 15 and 18. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the present Office Action, the limitation will be interpreted as “the first resin layer”.
Claims 2-11, and 14-22 are indefinite based on their dependency on claims 1 and 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 20220077114).
Regarding claim 1, Park teaches a semiconductor device Fig. 1: 10 comprising:
a substrate Fig. 1: 200 having a first surface (i.e. top surface);
a first spacer Fig. 1: 730 and a second spacer Fig. 1: 730 that are provided at different positions on the first surface;
a first semiconductor chip Fig. 1: 710 provided on the first surface so as to be disposed between the first spacer Fig. 1: 730 and the second spacer Fig. 1: 730; and
a stacked body Fig. 1: 300+400 that is provided above the first spacer Fig. 1: 730, the second spacer Fig. 1: 730, and the first semiconductor chip Fig. 1: 710 and in which a plurality of second semiconductor chips Fig. 1: 401 are stacked in a first direction (annotated Z) substantially perpendicular to the first surface,
wherein one of the second semiconductor chips Fig. 1: 420, which is provided on the lowermost second semiconductor chip Fig. 1: 410, is stacked with an offset relative to the lowermost second semiconductor chip Fig. 1: 410 in a second direction (annotated Y) substantially parallel to the first surface and perpendicular to a direction (annotated X) from the first spacer Fig. 1: 730 toward the second spacer Fig. 1: 730, and
a central position of the first semiconductor chip Fig. 1: 710 is separated from a central position of the lowermost second semiconductor chip Fig. 1: 410 in the second direction when viewed in the first direction (shown in annotated Fig. 1; W1).
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Regarding claim 2, Park teaches the semiconductor device according to claim 1, wherein the central position of the first semiconductor chip Fig. 1: 710 is separated from the central position of the lowermost second semiconductor chip Fig. 1: 410 in the second direction by 1/2 or more of an offset amount of the second semiconductor chip Fig. 1: 420 on the lowermost second semiconductor chip Fig. 1: 410 (see annotated W2 vs W1).
Regarding claim 3, Park teaches the semiconductor device according to claim 1, wherein an offset amount between each two of the second semiconductor chips Fig. 1: 401 in the second direction (annotated Y) is different for each of the second semiconductor chips Fig. 1: 401, the two second semiconductor chips Fig. 1: 401 being stacked adjacent to each other.
Regarding claim 4, Park teaches the semiconductor device according to claim 1, wherein the stacked body Fig. 1: 300+400 includes four of the second semiconductor chips Fig. 4: 401 (4 dies are stacked), the four second semiconductor chips Fig. 4: 401 being continuously stacked with offsets in the second direction (shown in Fig. 1).
Regarding claim 5, Park teaches the semiconductor device according to claim 4, wherein the stacked body Fig. 1: 300+400 includes at least one first chip group Fig.1: 400 including four of the second semiconductor chips Fig. 4: 401, the four second semiconductor chips Fig. 4: 401 being continuously stacked with offsets in the second direction (annotated Y), and at least one second chip group Fig. 1: 300 including four of the second semiconductor chips Fig. 1: 301, the second semiconductor chips Fig. 1: 301 being continuously stacked with offsets in a direction opposite the second direction, and the first Fig.1: 400 and second chip Fig. 1: 300 groups are alternately stacked.
Regarding claim 8, Park teaches the semiconductor device according to claim 1, wherein the first semiconductor chip Fig. 9: 710 has a substantially rectangular shape when viewed in the first direction (annotated Z, view is shown in Fig. 9), and the second direction (annotated Y) is a short side direction of the first semiconductor chip Fig. 9: 710.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220077114) as applied to claim 1 above, and further in view of Choi (US 20230413585).
Regarding claim 6, Choi teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 4, wherein the three upper second semiconductor chips Fig. 16: 400b-d among the four second semiconductor chips Fig. 16: 400a-d continuously stacked with offsets in the second direction each have a thickness of 20 μm or larger and 100 μm or smaller (para. 0040 teaches a range that falls within the range of the claimed invention; i.e. 15-40 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Choi in order to have stack, reducing the thickness of semiconductor ships to achieve high capacity and high performance of a multichip package (para. 0003).
Regarding claim 7, Choi teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 1, wherein the lowermost second semiconductor chip Fig. 16: 400a has a thickness of 40 μm or larger and 200 μm or smaller (para. 0039 teaches a range that includes the range of the claimed invention; i.e. 40-400 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Choi in order to have stack, having a lowermost second chip with a greater thickness in order to prevent cracks from occurring in the lowermost second chip (para. 0038).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220077114) as applied to claim 1 above, and further in view of Kyung et al. (US 20220149010).
Regarding claim 9, Kyung teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 1, wherein the first spacer Fig. 1: 300 and the second spacer Fig. 1: 300 (300-2) are disposed side by side in a third direction (D1) substantially perpendicular to both the first direction (D2) and the second direction (an upward direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung’s teachings in order to define a perimeter around the semiconductor chip to attain uniform distribution of a weight of the chip stack, and protect the semiconductor chip from external impact (para. 0034).
Regarding claim 11, Kyung teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 1, further comprising a dummy chip Fig. 2: 210+310 provided on the first spacer Fig. 2: 300, the second spacer Fig. 2: 300, and the first semiconductor chip Fig. 2: 200,
wherein the stacked body Fig. 2: 400 is provided on the dummy chip Fig. 2: 210+310.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung’s teachings in order to establish no electrical connection between the semiconductor chip and the spacer, and avoid any electrical signal leakage from the semiconductor chip (para. 0038).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220077114).
Regarding claim 10, Park teaches the semiconductor device according to claim 1:
wherein no spacers Fig. 9: 730 are provided beside the first semiconductor chip Fig. 9: 710 in the second direction.
Park shows in Fig. 9, wherein no spacers Fig. 9: 730 are provided beside the first semiconductor chip Fig. 9: 710 in the second direction (annotated below). In the claim 1 rejection above, and annotated Fig. 1, Examiner has annotated second direction (i.e. Y) to show a direction that is parallel to the first surface and perpendicular to a direction (i.e. X). However, it is also noted that a second direction annotated below is parallel to the first surface and perpendicular to another direction that is also parallel to the first surface. Park teaches there is no spacer in this direction.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have no spacers beside the first semiconductor chip in a direction parallel to the first surface in order to increase the number of passive devices that can be disposed in the stack package, improving the electrical characteristics of the stack package (para. 0062).
Claims 12-17, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220077114), and further in view of Kyung et al. (US 20220149010) and Kyung et al. (US 20240170456).
Regarding claim 12, Park teaches a semiconductor device Fig. 1: 10 comprising:
a substrate Fig. 1: 200 having a first surface (i.e. top surface);
a first spacer Fig. 1: 730 and a second spacer Fig. 1: 730 that are provided at different positions on the first surface;
a first semiconductor chip Fig. 1: 710 provided on the first surface so as to be disposed between the first spacer Fig. 1: 730 and the second spacer Fig. 1: 730;
a stacked body Fig. 1: 300+400 that is provided above the first spacer Fig. 1: 730, the second spacer Fig. 1: 730, and the first semiconductor chip Fig. 1: 710 and in which a plurality of second semiconductor chips Fig. 1: 401 are stacked in a first direction (annotated Z) substantially perpendicular to the first surface,
a first resin layer Fig. 1: 500 (para. 0022 teaches “epoxy molding compound”) provided to cover the substrate Fig. 1: 200 and the stacked body Fig. 1: 300+400, wherein the stacked body Fig. 1: 300+400 includes:
a third semiconductor chip Fig. 5: 310 that is one of the plurality of second semiconductor chips Fig. 5: 301;
a fourth semiconductor chip Fig. 5: 320 that is provided on the third semiconductor chip Fig. 5: 310 and that is one of the plurality of second semiconductor chips Fig. 5: 301;
a second resin layer Fig. 1: 735 that is different from the first layer Fig. 1: 500, the second resin layer Fig. 1: 735 being in physical contact with an upper surface of the first semiconductor chip Fig. 1: 710 and a lower surface of the third semiconductor chip Fig. 5: 310,
a third resin layer Fig. 5: 355 that is different from the first layer Fig. 1: 500, the third resin layer Fig. 5: 355 being in physical contact with an upper surface of the third semiconductor chip Fig. 5: 310 and a lower surface of the fourth semiconductor chip Fig. 5: 320,
when a direction perpendicular to the first direction and approximately parallel to the first surface is taken as a second direction (annotated Y), the third semiconductor chip Fig. 5: 310 and the fourth semiconductor chip Fig. 5: 320 are stacked in a manner in which a central position of the fourth semiconductor chip Fig. 5: 320 along the second direction is offset in the second direction relative to a central position of the third semiconductor chip Fig. 5: 310 along the second direction (shown in Fig. 1),
the first semiconductor chip and the third semiconductor chip are stacked in a manner in which a central position of the first semiconductor chip along the second direction is offset in the second direction relative to the central position of the third semiconductor chip along the second direction,
the first spacer and the second spacer are disposed side by side in a third direction
substantially perpendicular to both the first direction and the second direction, and
when viewed along the second direction, no spacers are provided at a position
overlapping with the first semiconductor chip Fig. 1: 710 (see Fig. 9).
Examiner has annotated second direction (i.e. Y) to show a direction that is parallel to the first surface and perpendicular to a direction (i.e. X). However, it is also noted that a second direction annotated below is parallel to the first surface and perpendicular to another direction that is also parallel to the first surface. Park teaches there is no spacer in this direction.
Kyung (US 20240170456) discloses the following claim limitations not disclosed by Park:
a second resin layer Fig. 13: 720,
a third resin layer Fig. 13: 730,
the first semiconductor chip Fig. 13: 200 and the third semiconductor chip Fig. 13: 310 are stacked in a manner in which a central position of the first semiconductor chip Fig. 13: 200 along the second direction Fig. 13: D3 is offset in the second direction Fig. 13: D3 relative to the central position of the third semiconductor chip Fig. 13: 310 along the second direction Fig. 13: D3 (shown in fig. 13).
Although Park teaches adhesive layers Fig. 1: 735 and Fig. 5: 355, Park doesn’t explicitly teach they are resin layers. However, Kyung (US 20240170456) teaches the bonding layers 720, 730, may include an epoxy resin.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung in order to provide a stacked package bonded using an epoxy resin with improved reliability and reduce damage applied to the upper pads by reducing the repulsive force by the lower pad (para. 0091).
Kyung (US 20220149010) discloses the following claim limitations not disclosed by Park:
the first spacer Fig. 1: 300-1 and the second spacer Fig. 1: 300-2 are disposed side by side in a third direction Fig. 1: D1 substantially perpendicular to both the first direction (i.e. direction perpendicular to upper surface of the substrate) and the second direction Fig. 1: D2.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung in order to use spacers on all sides to prevent a weight of the chip stack from being concentrated on the first semiconductor ship and protect it against external impact (para. 0034).
Regarding claim 13, Park teaches a semiconductor device Fig. 1: 10 comprising:
a substrate Fig. 1: 200 having a first surface (i.e. top surface);
a first spacer Fig. 1: 730 and a second spacer Fig. 1: 730 that are provided at different positions on the first surface;
a first semiconductor chip Fig. 1: 710 provided on the first surface so as to be disposed between the first spacer Fig. 1: 730 and the second spacer Fig. 1: 730;
a dummy chip that is provided above the first spacer, the second spacer, and the first semiconductor chip;
a stacked body Fig. 1: 300+400 that is provided on the dummy chip and in which a plurality of second semiconductor chips Fig. 1: 401 are stacked in a first direction (annotated Z) substantially perpendicular to the first surface,
a first resin layer Fig. 1: 500 provided to cover the substrate Fig. 1: 200 and the stacked body Fig. 1: 300+400, wherein the stacked body Fig. 1: 300+400 includes:
a third semiconductor chip Fig. 5: 310 that is one of the plurality of second semiconductor chips Fig. 5: 301;
a fourth semiconductor chip Fig. 5: 320 that is provided on the third semiconductor chip Fig. 5: 310 and that is one of the plurality of second semiconductor chips Fig. 5: 301;
a second resin layer Fig. 1: 735 that is different from the first layer Fig. 1: 500,
the second resin layer Fig. 1: 735 being in physical contact with an upper surface of the dummy chip and a lower surface of the third semiconductor chip Fig. 5: 310,
a third resin layer Fig. 5: 355 that is different from the first layer Fig. 1: 500, the third resin layer Fig. 5: 355 being in physical contact with an upper surface of the third semiconductor chip Fig. 5: 310 and a lower surface of the fourth semiconductor chip Fig. 5: 320,
when a direction perpendicular to the first direction and approximately parallel to the first surface is taken as a second direction (annotated Y), the third semiconductor chip Fig. 5: 310 and the fourth semiconductor chip Fig. 5: 320 are stacked in a manner in which a central position of the fourth semiconductor chip Fig. 5: 320 along the second direction is offset in the second direction relative to a central position of the third semiconductor chip Fig. 5: 310 along the second direction (shown in Fig. 1),
the first semiconductor chip and the third semiconductor chip are stacked in a manner in which a central position of the first semiconductor chip along the second direction is offset in the second direction relative to the central position of the third semiconductor chip along the second direction,
the first spacer and the second spacer are disposed side by side in a third direction
substantially perpendicular to both the first direction and the second direction, and
when viewed along the second direction, no spacers are provided at a position
overlapping with the first semiconductor chip Fig. 1: 710 (see Fig. 9).
Examiner has annotated second direction (i.e. Y) to show a direction that is parallel to the first surface and perpendicular to a direction (i.e. X). However, it is also noted that a second direction annotated below is parallel to the first surface and perpendicular to another direction that is also parallel to the first surface. Park teaches there is no spacer in this direction.
Kyung (US 20240170456) discloses the following claim limitations not disclosed by Park:
a second resin layer Fig. 13: 720,
a third resin layer Fig. 13: 730,
the first semiconductor chip Fig. 13: 200 and the third semiconductor chip Fig. 13: 310 are stacked in a manner in which a central position of the first semiconductor chip Fig. 13: 200 along the second direction Fig. 13: D3 is offset in the second direction Fig. 13: D3 relative to the central position of the third semiconductor chip Fig. 13: 310 along the second direction Fig. 13: D3 (shown in fig. 13).
Although Park teaches adhesive layers Fig. 1: 735 and Fig. 5: 355, Park doesn’t explicitly teach they are resin layers. However, Kyung (US 20240170456) teaches the bonding layers 720, 730, may include an epoxy resin.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung in order to provide a package with improved reliability and reduce damage applied to the upper pads by reducing the repulsive force by the lower pad (para. 0091).
Kyung (US 20220149010) discloses the following claim limitations not disclosed by Park:
a dummy chip Fig. 2: 210+310 that is provided above the first spacer Fig. 2: 300, the second spacer Fig. 2: 300, and the first semiconductor chip Fig. 2: 200 (shown in Fig. 2);
a stacked body Fig. 2: 400 that is provided on the dummy chip Fig. 2: 210+310,
the second resin layer Fig. 2: 420 being in physical contact with an upper surface of the dummy chip Fig. 2: 210+310;
the first spacer Fig. 1: 300 and the second spacer Fig. 1: 300 (300-2) are disposed side by side in a third direction Fig. 1: D1 substantially perpendicular to both the first direction (i.e. direction perpendicular to upper surface of the substrate) and the second direction Fig. 1: D2.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Kyung in order to use spacers on all sides to prevent a weight of the chip stack from being concentrated on the first semiconductor ship and protect it against external impact (para. 0034).
Regarding claim 14, Park teaches the semiconductor device according to claim 12, wherein when an offset amount is taken as a distance by which the fourth semiconductor chip is offset relative to the third semiconductor chip, the central position of the first semiconductor chip along the second direction is separated from the central position of the third semiconductor chip along the second direction by 1/2 or more of the offset amount in the second direction.
Park teaches another group of second semiconductor chips in the stacked body where the central position of a fourth semiconductor chip Fig. 1: 420 is offset relative to the third semiconductor chip Fig. 1: 410, the central position of the first semiconductor chip Fig. 1: 710 along the second direction is separated from the central position of the third semiconductor chip Fig. 1: 410 along the second direction by 1/2 or more of the offset amount in the second direction (see annotation below).
This interpretation can be applied to teach the claimed offset allowing the bonding pads of each semiconductor chip to exposed when stacked to form a zigzag shape in a vertical direction.
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Regarding claim 15, Park teaches the semiconductor device according to claim 12, wherein an offset amount between each two of the second semiconductor chips Fig. 4: 310 and Fig. 4: 320 in the second direction is different for each of the second semiconductor chips, the two second semiconductor chips being stacked adjacent to each other (shown in Fig. 4).
Regarding claim 16, Park teaches the semiconductor device according to claim 12, wherein the stacked body Fig. 1: 300+400 further includes:
a fifth semiconductor chip Fig. 5: 330 that is provided on the fourth semiconductor chip Fig. 5: 320 and that is one of the plurality of second semiconductor chips Fig. 5: 301;
a sixth semiconductor chip Fig. 5: 340 that is provided on the fifth semiconductor chip Fig. 5: 330 and that is one of the plurality of second semiconductor chips Fig. 5: 301;
a fourth resin layer Fig. 5: 350 that is different from the first layer Fig. 1: 500, the fourth resin layer Fig. 5: 350 being in physical contact with an upper surface of the fourth semiconductor chip Fig. 5: 320 and a lower surface of the fifth semiconductor chip Fig. 5: 330; and
a fifth resin layer Fig. 5: 355 that is different from the first layer Fig. 1: 500, the fifth resin layer Fig. 5: 355 being in physical contact with an upper surface of the fifth semiconductor chip Fig. 5: 330 and a lower surface of the sixth semiconductor chip Fig. 5: 340,
the fourth semiconductor chip Fig. 5: 320 and the fifth semiconductor chip Fig. 5: 330 are stacked in a manner in which a central position of the fifth semiconductor chip Fig. 5: 330 along the second direction is offset in the second direction relative to the central position of the fourth semiconductor chip Fig. 5: 320 along the second direction,
the fifth semiconductor chip Fig. 5: 330 and the sixth semiconductor chip Fig. 5: 340 are stacked in a manner in which a central position of the sixth semiconductor chip Fig. 5: 340 along the second direction is offset in the second direction relative to the central position of the fifth semiconductor chip Fig. 5: 330 along the second direction.
Kyung (US 20240170456) discloses the following claim limitations not disclosed by Park:
a fourth resin layer Fig. 13: 740,
a fifth resin layer Fig. 13: 750,
Although Park teaches adhesive layers Fig. 1: 735 and Fig. 5: 355, Park doesn’t explicitly teach they are resin layers. However, Kyung (US 20240170456) teaches the bonding layers 720, 730, may include an epoxy resin.
Regarding claim 17, Park teaches the semiconductor device according to claim 16, wherein the stacked body Fig. 1: 300+400 includes at least one first chip group Fig. 1: 300 including four of the second semiconductor chips, the four second semiconductor chips being continuously stacked with offsets in the second direction, and at least one second chip group Fig. 1: 400 including four of the second semiconductor chips, the second semiconductor chips being continuously stacked with offsets in a direction opposite the second direction, and the first and second chip groups Fig. 1: 300+400 are alternately stacked (shown in Fig. 1).
Regarding claim 20, Park teaches the semiconductor device according to claim 12, wherein the first semiconductor chip Fig. 9: 710 has a substantially rectangular shape when viewed in the first direction, and the second direction is a short side direction of the first semiconductor chip Fig. 9: 710 (shown in Fig. 9).
Regarding claim 22, Park teaches the semiconductor device according to claim 16:
wherein when an offset Fig. 5: D2 amount is taken as a distance by which the fourth semiconductor chip Fig. 5: 320 is offset relative to the third semiconductor chip Fig. 5: 310, and
the central position of the first semiconductor chip along the second direction is separated from the central position of the third semiconductor chip along the second direction by approximately twice the offset amount.
Kyung (US 20240170456) discloses the following claim limitations not disclosed by Park:
the central position of the first semiconductor chip Fig. 13: 200 along the second direction Fig. 13: D3 is separated from the central position of the third semiconductor chip Fig. 13: 310 along the second direction by approximately twice the offset amount (shown in Fig. 13).
Claims 18, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220077114), Kyung et al. (US 20220149010), and Kyung et al. (US 20240170456) as applied to claim 12 above, and further in view of Choi (US 20230413585).
Regarding claim 18, Choi teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 16, wherein the three upper second semiconductor chips Fig. 16: 400b-d among the four second semiconductor chips Fig. 16: 400a-d continuously stacked with offsets in the second direction each have a thickness of 20 μm or larger and 100 μm or smaller (para. 0040 teaches a range that falls within the range of the claimed invention; i.e. 15-40 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Choi in order to have stack, reducing the thickness of semiconductor ships to achieve high capacity and high performance of a multichip package (para. 0003).
Regarding claim 19, Choi teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 12, wherein the third semiconductor chip Fig. 16: 400a has a thickness of 40 μm or larger and 200 μm or smaller (para. 0039 teaches a range that includes the range of the claimed invention; i.e. 40-400 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Choi in order to have stack, having a lowermost second chip with a greater thickness in order to prevent cracks from occurring in the lowermost second chip (para. 0038).
Regarding claim 21, Choi teaches the following claim limitations not disclosed by Park:
the semiconductor device according to claim 12, wherein a thickness of the third semiconductor chip Fig. 16: 400a is larger than a thickness of the fourth semiconductor chip Fig. 16: 400b (para. 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park with Choi in order to have stack, having a lowermost second chip with a greater thickness in order to prevent cracks from occurring in the lowermost second chip (para. 0038).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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