Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-4, 6-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2025/0021800) in view of Haykal et al (US 2023/0409889, herein Haykal).
Regarding claim 1, Xu teaches a neural network accelerator, comprising:
a control circuit configured to control a learning operation for a neural network by performing a plurality of learning steps ([0002], [0098], machine learning in neural network) ;
an operation processor configured to perform the learning operation under the control of the control circuit (Fig 1, [0013-0014], processor to implement neural network); and
an operation memory coupled to the operation processor ([0014], memory devices),
wherein the operation processor performs a first embedding operation using an embedding entry required for a current learning step, and performs a second embedding operation using an embedding entry that is required for a next learning step and is not affected by the current learning step ([0043], [0045], [0063], [0066-0067], embedding layer of neural network operations, [0051], updating embedded sequences independently of each other in subsequent or concurrent time steps).
Xu fails to teach wherein the memory stores an embedding table.
Haykal teaches a neural network accelerator comprising an operation processor and an operation memory storing an embedding table and coupled to the operation processor ([0023-0024], [0045], memory storing embedding tables & machine learning accelerator).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Xu and Haykal to utilize embedding tables. While Xu does not explicitly state that the embedding layer of the exemplary layer may utilize embedding tables, Xu does disclose the use of embedded sequences containing the data to be used in the embedding layer of a neural network. As both Xu and Haykal disclose performing neural network operations that include an embedding layer, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Xu and Haykal teaches the neural network accelerator of claim 1, wherein the embedding table stores state data corresponding to a current state of an embedding entry (Haykal [0023-0024], [0047-0050], embedding tables storing parameters and learning model states).
Regarding claim 3, the combination of Xu and Haykal teaches the neural network accelerator of claim 2, wherein the operation processor sets a state of a given embedding entry in an initial state to an embedding state when the first embedding operation is performed on the given embedding entry, and the operation processor sets the state of the given embedding entry in the embedding state to the initial state after an update operation is performed on the given embedding entry (Xu [0081], [0087], matrix values representing updated embedded values for embedding layer, Haykal [0023-0024], [0047-0050], embedding tables storing parameters and learning model states).
Regarding claim 4, the combination of Xu and Haykal teaches the neural network accelerator of claim 2, wherein the operation processor sets a state of a given embedding entry in an initial state to a first proactive state when the second embedding operation is performed on the given embedding entry (Xu [0081], [0087], matrix values representing updated embedded values for embedding layer, Haykal [0023-0024], [0047-0050], embedding tables storing parameters and learning model states)
Regarding claim 6, the combination of Xu and Haykal teaches the neural network accelerator of claim 1, wherein the operation memory stores first input data used for the current learning step and second input data for the next learning step, and wherein the operation processor determines the embedding entry required for the second embedding operation by referring to the first input data and the second input data (Xu [0017], input sequences for neural network operations, [0043], embedding layer, [0051], updating embedded sequences independently of each other in subsequent or concurrent time steps).
Claims 7-10 and 12 refer to a method embodiment of the accelerator embodiment of claims 1-4 and 6, respectively. Therefore, the above rejections for claims 1-4 and 6 are applicable to claims 7-10 and 12, respectively.
Allowable Subject Matter
3. Claims 5 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nagarajan (US 2023/0153116) discloses a processor that utilizes embedding tables to process embedding layers of a neural network.
Agrawal (US 2023/0127453) discloses a processor wherein neural network layers are computed independently of previous operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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