DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2022-0167036, filed on 12/02/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/27/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR PACKAGE INCLUDING A LOWER REDISTRIBUTION STRUCTURE, AN UPPER REDISTRIBUTION STRUCTURE AND A HEAT DISSIPATION PLATE IN THE UPPER REDISTRIBUTION STRUCTURE”.
Appropriate correction is required.
Claim Objections
Claims 16-17 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
Regarding claim 16, “the primary conductive structure” on line 16 and “the secondary conductive structure” on lines 16-17 lack antecedent bases. The Examiner believes that these issues are caused by typos, as similar structures are introduced as “a first conductive structure” on line 11 and “a second conductive structure” on line 12, respectively. Therefore, for examining purpose, “the first conductive structure” is considered to be “the first conductive structure”, and “the secondary conductive structure” is considered to be “the second conductive structure”.
Regarding claim 17, “the primary conductive structure” on lines 2 and 4, and “the secondary conductive structure” on lines 5-6 lack antecedent bases. The Examiner believes that these issues are caused by typos, as similar structures are introduced in claim 16 as “a first conductive structure” on line 11 and “a second conductive structure” on line 12, respectively. Therefore, for examining purpose, “the first conductive structure” is considered to be “the first conductive structure”, and “the secondary conductive structure” is considered to be “the second conductive structure”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2018/0197831 A1).
Regarding claim 1, Kim teaches a semiconductor package (semiconductor package, Fig. 9, [0132]-[0133]), comprising:
a lower redistribution structure (second redistribution layer 20b, Figs. 6, [0113], shown as the lower distribution structure in Illustrative Fig. 1 which is an annotated version of Fig. 9);
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a semiconductor device (electronic device 1, Fig. 6, [0112], shown as semiconductor device in Illustrative Fig. 1) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 1);
a lower encapsulant (insulating member 49a, Figs. 4, [0114], shown as lower encapsulant in Illustrative Fig. 1) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 1) and surrounding a side surface of the semiconductor device (semiconductor device, Illustrative Fig. 1); and
an upper composite redistribution structure (comprising first redistribution layer 20a (Fig. 6, [0116], labeled as primary conductive structure in Illustrative Fig. 1, and the layer with electrical connections (not described by Kim) shown as secondary conductive structure in Illustrative Fig. 1) disposed on an upper portion (upper surface) of the semiconductor device (semiconductor device, Illustrative Fig. 1),
wherein the upper composite redistribution structure (comprising the primary conductive structure and secondary conductive structure, Illustrative Fig. 1) includes:
a primary conductive structure (primary conductive structure, Illustrative Fig. 1);
a secondary conductive structure (secondary conductive structure, Illustrative Fig. 1) disposed on the primary conductive structure (primary conductive structure, Illustrative Fig. 1);
connection vias (connection vias, Illustrative Fig. 1) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 1) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 1); and
an upper encapsulant (first insulating protective layer 30a, Fig. 6, [0117], shown as upper encapsulant in Illustrative Fig. 1) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 1) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 1) and surrounding the connection vias (connection vias, Illustrative Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4, 6, 8-9, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) as applied to claim 1 above, and further in view of Kang (US 2021/0118765 A1).
Regarding claim 2, Kim teaches the semiconductor package of claim 1, wherein the primary conductive structure (first redistribution layer 20a as the primary conductive structure in Illustrative Fig. 1) includes a redistribution structure ([0064]-[0065]: first redistribution layer 20a is a redistribution layer and therefore includes a redistribution structure).
Kim, however, does not teach that the semiconductor package of claim 1 further comprises
a connection pad electrically connected to each of the connection vias and disposed on the secondary conductive structure.
Kang, on the other hand teaches a semiconductor package (semiconductor package 100H, Fig. 21, [0090]) comprising a primary conductive structure (bottommost redistribution layer, Fig. 21, [0025]), a secondary conductive structure (topmost redistribution layer 142, Fig. 21, [0025]), and connection vias (vias in the top redistribution via layers 143, Fig. 21, [0040]), wherein a connection pad (uppermost redistribution pattern 142P, Fig. 21, [0047]) electrically connected to each of the connection vias (vias in the top redistribution via layers 143, Fig. 21) and disposed on the secondary conductive structure (topmost redistribution layer 142, Fig. 21, [0025]).
Kang further discloses that having an uppermost redistribution pattern 142P of the plurality of redistribution patterns 142P protrude from the second surface S2 of the interconnect structure 140 (Fig. 21) provides the benefit ([0047]) of easily mounting and sufficiently securing the electronic components (passive component 125, [0047]). Furthermore, using connection pads on the connective layers is a standard method in electronics to provide a large and protruding connection structure for mounting electronic devices on packages and wiring layers. Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim to include connection pads on the secondary connection structure and connected to connection vias to obtain the benefit of obtaining a connection pad for upper semiconductor devices which would facilitate easy and secure mounting of the upper semiconductor devices.
Thus, the combination of Kim and Kang meets all the limitations of claim 2.
Regarding claim 3, Kim in view of Kang teaches the semiconductor package of claim 2, wherein
Kim further teaches that the secondary conductive structure (electrical connections (not described by Kim) labeled as secondary conductive structure in Illustrative Fig. 1) does not include a redistribution structure (Illustrative Fig. 1: secondary conductive structures include only pads (after modification of Kim by Kang, see claim 2 rejection above) for mounting the upper semiconductor devices and therefore do not include redistribution structures).
Regarding claim 4, Kim in view of Kang teaches the semiconductor package of claim 3, wherein side surfaces of the primary conductive structure (primary conductive structure, Illustrative Fig. 1), the secondary conductive structure (secondary conductive structure, Illustrative Fig. 1), and the upper encapsulant (upper encapsulant, Illustrative Fig. 1) are aligned with one another to form a coplanar surface (Illustrative Fig. 1: side surfaces form the vertical side walls of the semiconductor package).
Regarding claim 6, Kim in view of Kang teaches the semiconductor package of claim 3, wherein
Kim also teaches that the semiconductor package further comprises
a heat dissipation plate (heat dissipating conductor 48a labeled as heat dissipation plate in Illustrative Fig. 1, [0077]-[0078]) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 1) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 1),
wherein first heat dissipation vias (via connections attached to the heat dissipation plate, see first heat dissipation vias in Illustrative Fig. 1) passing through the primary conductive structure (primary conductive structure, Illustrative Fig. 1) are disposed in the primary conductive structure (primary conductive structure, Illustrative Fig. 1), and
wherein one end (bottom) of each of the first heat dissipation vias (first heat dissipation via, Illustrative Fig. 1) is in contact with a top surface of the semiconductor device (semiconductor device, Illustrative Fig. 1), and the other end (top) of each of the first heat dissipation vias (first heat dissipation via, Illustrative Fig. 1) is connected to a bottom surface of the heat dissipation plate (heat dissipation plate, Illustrative Fig. 1).
Regarding claim 8, Kim in view of Kang teaches the semiconductor package of claim 6, wherein
Kim further teaches that the heat dissipation plate (heat dissipation plate, Illustrative Fig. 1) is spaced apart from the connection vias (connection vias, Illustrative Fig. 1) and a side surface of the heat dissipation plate (heat dissipation plate, Illustrative Fig. 1) is surrounded by the upper encapsulant (upper encapsulant in Illustrative Fig. 1).
Regarding claim 9, Kim in view of Kang teaches the semiconductor package of claim 6, wherein
the combination of Kim and Kang (the semiconductor package of Kim modified by Kang (see claim 2 rejection above) repeats the vias and pads of the primary conductive structure in the secondary conductive structure) further teaches that the heat dissipation plate (heat dissipating conductor 48a labeled as heat dissipation plate in Illustrative Fig. 1) comprises a same material ([0049]: “Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, or alloys thereof”) as the connection vias (connection vias, Illustrative Fig. 1).
Regarding claim 11, while Kim in view of Kang teaches the semiconductor package of claim 8,
Kim does not teach that
second heat dissipation vias passing through the secondary conductive structure are disposed in the secondary conductive structure, and
one end of each of the second heat dissipation vias is in contact with the heat dissipation plate.
Kang, on the other hand, teaches a semiconductor package (semiconductor package 100H, Fig. 21, [0090]), comprising a lower redistribution structure (backside wiring layer 132, Fig. 21, [0025]), a semiconductor device (second semiconductor chip 122, Fig. 21, [022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21), a lower encapsulant (first encapsulant 131, Fig. 21, [0022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21) and surrounding a side surface of the semiconductor device (both left and right side-surfaces of second semiconductor chip 122, Fig. 21), an upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]) disposed on the semiconductor device (second semiconductor chip 122, Fig. 21), wherein the upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]: “interconnect structure 140 may include more or fewer of the insulating layers, the redistribution layers, and the redistribution via layers than the example illustrated in the diagram”) comprises a primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21, [0040]), a secondary conductive structure (topmost redistribution layer 142, Fig. 21, [0025]) disposed on an upper portion of the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), connection vias (vias in the top redistribution via layers 143, Fig. 21, [0040]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21), a heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21, [0031]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and laterally spaced apart from the connection vias (vias in the top redistribution via layers 143, Fig. 21), an upper encapsulant (topmost insulating layer 141, Fig. 21, [0057]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and surrounding the connection vias (vias in the topmost redistribution via layers 143, Fig. 21) and a side surface of the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21), first heat dissipation vias (heat dissipation via 143HV in the bottommost and middle redistribution via layers 143, Fig. 21, [0044]) passing through the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), and having one end contacting a top surface of the semiconductor device (second semiconductor chip 122, Fig. 21) and the other end contacting the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21). Kang further teaches
second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21) passing through the secondary conductive structure (topmost redistribution layer 142, Fig. 21) disposed in the secondary conductive structure (topmost redistribution layer 142, Fig. 21); and
having one end (bottom end) of each of the second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21) in contact with the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21, [0031]).
Kang further discloses that having the heat dissipation pattern 142 HP and heat dissipation vias 143HV helps to transfer the heat from the semiconductor device to the heat dissipation member 127 ([0045]), and furthermore exposing the heat dissipation member 127 on the upper surface of the package improves heat dissipation efficiency ([0045]-[0046]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package of Kang is analogous to the semiconductor package of Kim in view of Kang, and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim in view of Kang to include connection vias through the upper encapsulant layer contacting the heat dissipation plate, and a heat dissipation pad (such as the heat dissipation pattern 142HP and heat dissipation member 127 of Kang) on the secondary conductive structure, as taught by Kang, to improve the efficiency of heat dissipation from the semiconductor device. Thus, the combination of Kim and Kang teaches that (see Illustrative Fig. 2 as an illustration of the semiconductor package of Kim in view of Kang modified by Kang)
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second heat dissipation vias passing through the secondary conductive structure are disposed in the secondary conductive structure, and
one end of each of the second heat dissipation vias is in contact with the heat dissipation plate.
Regarding claim 12, Kim in view of Kang teaches the semiconductor package of claim 11, wherein
the combination of Kim and Kang (Illustrative Fig. 2) further teaches that each of the second heat dissipation vias (heat dissipation vias 143HV in the topmost redistribution layer 142, see Fig. 21 in Illustrative Fig. 2) has a tapered shape (Illustrative Fig. 2) in which a width of each of the second heat dissipation vias (heat dissipation vias 143HV in the topmost redistribution layer 142, Illustrative Fig. 2) in a horizontal direction increases farther away from the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, see Fig. 21 of Illustrative Fig. 2).
Regarding claim 13, while Kim in view of Kang teaches the semiconductor package of claim 11,
Kim is silent about a heat dissipation pad and therefore does not teach that the semiconductor package further comprises a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface connected to the other end of each of the second heat dissipation vias.
Kang, however, teaches a heat dissipation pad (heat dissipation pattern 142HP in the top redistribution layer 142, Fig. 21, [0035]) disposed on the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and having a bottom surface contacting the other end (top end) of each of the second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21).
Kang further discloses that having the heat dissipation pattern 142 HP and heat dissipation vias 143HV helps to transfer the heat from the semiconductor device to the heat dissipation member 127 ([0045]), and furthermore exposing the heat dissipation member 127 on the upper surface of the package improves heat dissipation efficiency ([0045]-[0046]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package of Kang is analogous to the semiconductor package of Kim, and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim to include connection vias through the upper encapsulant layer contacting the heat dissipation plate, and a heat dissipation pad (such as the heat dissipation pattern 142HP and heat dissipation member 127 of Kang) on the secondary conductive structure, as taught by Kang, to improve the efficiency of heat dissipation from the semiconductor device. Thus, the combination of Kim and Kang teaches that the semiconductor package further comprises (see Illustrative Fig. 2 as an illustration of the semiconductor package of Kim modified by Kang) a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface connected to the other end of each of the second heat dissipation vias.
Regarding claim 14, Kim in view of Kang teaches the semiconductor package of claim 13, wherein
the combination of Kim in view of Kang (see Illustrative Fig. 2) further teaches that
a thickness of each of the connection pads (heat dissipation pattern 142HP in the top redistribution layer 142, Fig. 21 of Illustrative Fig. 2) in a vertical direction is equal to a thickness of the heat dissipation pad (connection pattern 142P in the top redistribution layer 142, Fig. 21 of Illustrative Fig. 2) in the vertical direction (vertical direction in Illustrative Fig. 2), and
the heat dissipation pad (heat dissipation pattern 142HP in the top redistribution layer 142, Fig. 21 of Illustrative Fig. 2) comprises a same material (Kang, [0042]: “copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.”, and therefore a person of ordinary skill in the art would also use the same material for the connection pads and heat dissipation pad in the semiconductor package of Kim in view of Kang which would provide the benefit of simplifying the manufacturing) as the connection pads (connection pattern 142P in the top redistribution layer 142, Fig. 21 of Illustrative Fig. 2).
Regarding claim 15, Kim in view of Kang teaches the semiconductor package of claim 13, wherein
the combination of Kim and Kang teaches that the connection vias, the first heat dissipation vias, the heat dissipation plate, the second heat dissipation vias, and the heat dissipation pad comprise copper (Cu) (Kim, [0049]: “The interlayer connection conductor 48 may be formed of a conductive material such as Cu” where all connection vias, the first heat dissipation vias, the heat dissipation plate, the second heat dissipation vias, and the heat dissipation pad are made from the same material).
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) in view of Kang (US 2021/0118765 A1) as applied to claims 2-4, 6, 8-9, and 11-15 above, and further in view of Min (US 2016/0276308 A1).
Regarding claim 5, Kim in view of Kang teaches the semiconductor package of claim 3, wherein
the semiconductor device (semiconductor device, Illustrative Fig. 1) includes a logic device ([0145]: “an integrated circuit”; integrated circuits typically perform logic operations, and therefore include logic circuits), and
the semiconductor package further comprises an upper semiconductor device (electronic component 300 shown as upper semiconductor device in Illustrative Fig. 1, [0135]: “The electronic component 300 may be an active … device.”) electrically connected to the connection pads (the semiconductor package of Kim in view of Kang includes connection pads for connecting the upper semiconductor devices (see claim 2 rejection above)), mounted on the upper composite redistribution structure (comprising primary conductive structure and secondary conductive structure, Illustrative Fig. 1 ).
Kim and Kang, however, are silent on that
the upper semiconductor device includes a memory device.
Min, on the other hand, teaches a semiconductor package (package-on-package (POP) structure 300, Fig. 3A, [0071]), which is analogous to the semiconductor package of Kim in view of Kang in that the package comprises a semiconductor device (semiconductor device 115, Fig. 3A, [0044]: “a memory controller semiconductor device” which is a logic device) that generates heat and an upper second semiconductor device (first semiconductor device 140, Fig. 3A, [0077]), wherein
upper semiconductor device includes a memory device ([0077]: DRAM).
A person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to form a semiconductor device package comprising a memory controller device (logic device) that generates heat and a memory device (DRAM) that is controlled by the memory controller would be motivated to use the memory controller as the semiconductor device and the memory device as the upper semiconductor device, as taught by Min, in the semiconductor package of Kim in view of Kang to facilitate effective heat dissipation.
Thus, the combination of Kim, Kang, and Min meets all the limitations of claim 5.
Regarding claim 10, while Kim in view of Kang teaches the semiconductor package of claim 8,
both Kim and Kang are silent about a hot spot and therefore do not teach that a part of the semiconductor device is a hot spot that generates relatively high heat as compared to other parts thereof when the semiconductor device is operating, and the heat dissipation plate and the first heat dissipation vias are arranged on a vertical upper portion of the hot spot.
Min, on the other hand, teaches a semiconductor package (package-on-package (POP) structure 300, Fig. 3A, [0071]), which is analogous to the semiconductor package of Kim in view of Kang in that the package comprises a semiconductor device (semiconductor device 115, Fig. 3A, [0044]) that generates heat, an upper second semiconductor device (first semiconductor device 140, Fig. 3A, [0077]), and a heat dissipating vias (thermal vias 130 and a heat slug 350, Fig. 3A, [0082]), wherein a part of the semiconductor device (semiconductor device 115, Fig. 3A) is a hot spot ([0082]) that generates relatively high heat as compared to other parts (Fig. 3A, [0082]: “The carved heat slug 350 is mounted to be substantially centered over the thermal hot spots of a semiconductor device 115”, and therefore the semiconductor device has hot spots with relatively high heat compared to other parts) thereof when the semiconductor device is operating (heat is generated during operation of the device), and the heat dissipation plate (heat slug 350, Fig. 3) and the first heat dissipation vias (thermal vias 130, Fig. 3: thermal vias 130 and heat slug 350 are horizontally aligned ) are arranged on a vertical upper portion of the hot spot ([0082]: “The carved heat slug 350 is mounted to be substantially centered over the thermal hot spots of a semiconductor device 115”, and therefore, the heat dissipations vias and heat dissipation vias are arranged on a vertical upper portion of the hot spot).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package of Kim in view of Kang is analogous to the semiconductor package of Min, and therefore, would be motivated to form the heat dissipation plate and the first heat dissipation vias in the semiconductor package of Kim in view of Kang centered on the hot spot of the semiconductor device that generates relatively high heat as compared to other parts thereof when the semiconductor device is operating, as taught by Min, to be able to dissipate the heat most effectively by transferring the heat directly from the hot spots.
Thus, the combination of Kim, Kang and Min meets of the limitations of claim 10.
Claim 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) in view of Kang (US 2021/0118765 A1).
Regarding claim 16, Kim teaches a semiconductor package (semiconductor package, Fig. 9, [0132]-[0133]), comprising:
a lower redistribution structure (second redistribution layer 20b, Figs. 6, [0113], shown as the lower distribution structure in Illustrative Fig. 3, which is an annotated version of Fig. 9);
a semiconductor device (electronic device 1, Fig. 6, [0112], shown as semiconductor device in Illustrative Fig. 3) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 3);
a lower encapsulant (insulating member 49a, Figs. 4, [0114], shown as lower encapsulant in Illustrative Fig. 3) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 3) and surrounding a side surface of the semiconductor device (semiconductor device, Illustrative Fig. 3);
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an upper composite redistribution structure (comprising first redistribution layer 20a (Fig. 6, [0116], labeled as first conductive structure in Illustrative Fig. 1, and the layer with electrical connections (not described by Kim) shown as second conductive structure in Illustrative Fig. 1) disposed on an upper portion of the semiconductor device (semiconductor device, Illustrative Fig. 3); and
conductive posts (interlayer connection conductors 48 (Figs. 3 and 9, labeled as conductive posts in Illustrative Fig. 3, [0116]) electrically connecting the upper composite redistribution structure (comprising first conductive structure and second conductive structure, Illustrative Fig. 3) with the lower redistribution structure (lower distribution structure, Illustrative Fig. 3) and spaced apart from the semiconductor device (semiconductor device, Illustrative Fig. 3),
wherein the upper composite redistribution structure (comprising first conductive structure and second conductive structure, Illustrative Fig. 3) includes:
a first conductive structure (first conductive structure, Illustrative Fig. 3);
a second conductive structure (second conductive structure, Illustrative Fig. 3) disposed on an upper portion of the first conductive structure (first conductive structure, Illustrative Fig. 3);
connection vias (connection vias, Illustrative Fig. 3) disposed between the first conductive structure (first conductive structure, Illustrative Fig. 3) and the second conductive structure (first conductive structure, Illustrative Fig. 3);
an upper encapsulant (first insulating protective layer 30a, Fig. 6, [0117], shown as upper encapsulant in Illustrative Fig. 3) disposed between the primary conductive structure (first conductive structure, Illustrative Fig. 3) and the secondary conductive structure (second conductive structure, Illustrative Fig. 3) and surrounding a side surface of the connection vias (connection vias, Illustrative Fig. 3).
Kim, however, does not teach
a connection pad electrically connected to each of the connection vias and disposed on the second conductive structure.
Kang, on the other hand teaches a semiconductor package (semiconductor package 100H, Fig. 21, [0090]) comprising a first conductive structure (bottommost redistribution layer, Fig. 21, [0025]), a second conductive structure (topmost redistribution layer 142, Fig. 21, [0025]), and connection vias (vias in the top redistribution via layers 143, Fig. 21, [0040]), wherein a connection pad (uppermost redistribution pattern 142P, Fig. 21, [0047]) electrically connected to each of the connection vias (vias in the top redistribution via layers 143, Fig. 21) and disposed on the second conductive structure (topmost redistribution layer 142, Fig. 21, [0025]).
Kang further discloses that having an uppermost redistribution pattern 142P of the plurality of redistribution patterns 142P protrude from the second surface S2 of the interconnect structure 140 (Fig. 21) provides the benefit ([0047]) of easily mounting and sufficiently securing the electronic components (passive component 125, [0047]). Furthermore, using connection pads on the connective layers is a standard method in electronics to provide a large and protruding connection structure for mounting electronic devices on packages and wiring layers. Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim to include connection pads on the second connection structure and connected to connection vias to obtain the benefit of obtaining a connection pad for upper semiconductor devices which would facilitate easy and secure mounting of the upper semiconductor devices.
Thus, the combination of Kim and Kang meets all the limitations of claim 16.
Regarding claim 17, Kim in view of Kang teaches the semiconductor package of claim 16, wherein
Kim teaches that the semiconductor package further comprises:
first heat dissipation vias (via connections attached to the heat dissipating conductor 48a (labeled as heat dissipation plate in Illustrative Fig. 3), see first heat dissipation vias in Illustrative Fig. 3) passing through the primary conductive structure (first conductive structure, Illustrative Fig. 3) and having one end (bottom) thereof contacting a top surface of the semiconductor device (semiconductor device, Illustrative Fig. 3);
a heat dissipation plate (heat dissipating conductor 48a labeled as heat dissipation plate in Illustrative Fig. 3, [0077]-[0078]) disposed between the primary conductive structure (first conductive structure, Illustrative Fig. 3) and the secondary conductive structure (second conductive structure, Illustrative Fig. 3) and connected to the other end (top) of each of the first heat dissipation vias (first heat dissipation vias, Illustrative Fig. 3).
Kim, however, does not teach
second heat dissipation vias passing through the secondary conductive structure and having one end contacting the heat dissipation plate; and
a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface contacting the other end of each of the second heat dissipation vias.
Kang, on the other hand, teaches a semiconductor package (semiconductor package 100H, Fig. 21, [0090]), comprising a lower redistribution structure (backside wiring layer 132, Fig. 21, [0025]), a semiconductor device (second semiconductor chip 122, Fig. 21, [022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21), a lower encapsulant (first encapsulant 131, Fig. 21, [0022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21) and surrounding a side surface of the semiconductor device (both left and right side-surfaces of second semiconductor chip 122, Fig. 21), an upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]) disposed on the semiconductor device (second semiconductor chip 122, Fig. 21), wherein the upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]: “interconnect structure 140 may include more or fewer of the insulating layers, the redistribution layers, and the redistribution via layers than the example illustrated in the diagram”) comprises a first conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21, [0040]), a second conductive structure (topmost redistribution layer 142, Fig. 21, [0025]) disposed on an upper portion of the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), connection vias (vias in the top redistribution via layers 143, Fig. 21, [0040]) disposed between the first conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the second conductive structure (topmost redistribution layer 142, Fig. 21), a heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21, [0031]) disposed between the first conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the second conductive structure (topmost redistribution layer 142, Fig. 21), an upper encapsulant (topmost insulating layer 141, Fig. 21, [0057]) disposed between the first conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the second conductive structure (topmost redistribution layer 142, Fig. 21) and surrounding the connection vias (vias in the topmost redistribution via layers 143, Fig. 21) and a side surface of the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21), first heat dissipation vias (heat dissipation via 143HV in the bottommost and middle redistribution via layers 143, Fig. 21, [0044]) passing through the first conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), and having one end contacting a top surface of the semiconductor device (second semiconductor chip 122, Fig. 21) and the other end contacting the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21). Kang further teaches
second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21) passing through the secondary conductive structure and having one end (bottom end) contacting the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21, [0031]); and
a heat dissipation pad (heat dissipation pattern 142HP in the top redistribution layer 142, Fig. 21, [0035]) disposed on the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and having a bottom surface contacting the other end (top end) of each of the second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21).
Kang further discloses that having the heat dissipation pattern 142 HP and heat dissipation vias 143HV helps to transfer the heat from the semiconductor device to the heat dissipation member 127 ([0045]), and furthermore exposing the heat dissipation member 127 on the upper surface of the package improves heat dissipation efficiency ([0045]-[0046]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package of Kang is analogous to the semiconductor package of Kim in view of Kang, and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim in view of Kang to include connection vias through the upper encapsulant layer contacting the heat dissipation plate, and a heat dissipation pad (such as the heat dissipation pattern 142HP and heat dissipation member 127 of Kang) on the secondary conductive structure, as taught by Kang, to improve the efficiency of heat dissipation from the semiconductor device. Thus, the combination of Kim and Kang teaches that (see Illustrative Fig. 4 as an illustration of the semiconductor package of Kim in view of Kang modified by Kang)
second heat dissipation vias passing through the secondary conductive structure and having one end contacting the heat dissipation plate; and
a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface contacting the other end of each of the second heat dissipation vias.
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) in view of Kang (US 2021/0118765 A1) as applied to claims 16-17 above, and further in view of Chuang (US 2021/0343665 A1).
Regarding claim 18, Kim in view of Kang teaches the semiconductor package of claim 16, wherein
Kim and Kang do not teach that the semiconductor device comprises two or more semiconductor devices laterally spaced apart from each other.
Chuang, on the other hand, teaches a semiconductor package (Fig. 2D, [0092]) with thermal vias (thermal pillars 207, Fig. 2D, [0092]) for providing heat dissipation for a semiconductor device, wherein the semiconductor device (comprising first semiconductor device 109 and second semiconductor device 111, Fig. 2D, [0092]) comprises two (first semiconductor device 109 and second semiconductor device 111, Fig. 2D) or more semiconductor devices laterally spaced apart from each other (Fig. 2D: first semiconductor device 109 and second semiconductor device 111 are spatially separated).
Chuang further discloses that the first semiconductor device 109 and second semiconductor device 111 may be utilized together ([0087]), and the heat generated by the second semiconductor device 111 can be removed separately by thermal vias 201 and thermal caps 205 (Fig. 2D, [0087]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to use a semiconductor device comprising multiple circuits with different levels of heat generation in the semiconductor package of Kim in view of Kang would be motivated to separate the semiconductor device in to two or more semiconductor devices that are laterally spaced apart from each other, as thought by Chuang, which would provide the benefit of preventing the semiconductor device with high heat generation to affect the other semiconductor device (see Chuang, Fig. 2F where alternatively two semiconductor devices are combined as a single device ([0092])).
Thus, the combination of Kim, Kang, and Chuang meets al the limitations of claim 18.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) in view of Kang (US 2021/0118765 A1) as applied to claims 16-17 above, and further in view of Min (US 2016/0276308 A1).
Regarding claim 19, Kim in view of Kang teaches the semiconductor package of claim 17, wherein
the semiconductor device (semiconductor device, Illustrative Fig. 3) includes a logic device ([0145]: “an integrated circuit”; integrated circuits typically perform logic operations, and therefore include logic circuits), and
the semiconductor package further comprises an upper semiconductor device (electronic component 300 shown as upper semiconductor device in Illustrative Fig. 3, [0135]: “The electronic component 300 may be an active … device.”) disposed on the upper composite redistribution structure (comprising first conductive structure and second conductive structure, Illustrative Fig. 3), electrically connected to the connection pads (the semiconductor package of Kim in view of Kang includes connection pads for connecting the upper semiconductor devices (see claim 16 rejection above)),
Kim and Kang, however, are silent on that
the upper semiconductor device includes a memory device.
Min, on the other hand, teaches a semiconductor package (package-on-package (POP) structure 300, Fig. 3A, [0071]), which is analogous to the semiconductor package of Kim in view of Kang in that the package comprises a semiconductor device (semiconductor device 115, Fig. 3A, [0044]: “a memory controller semiconductor device” which is a logic device) that generates heat and an upper second semiconductor device (first semiconductor device 140, Fig. 3A, [0077]), wherein
upper semiconductor device includes a memory device ([0077]: DRAM).
A person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to form a semiconductor device package comprising a memory controller device (logic device) that generates heat and a memory device (DRAM) that is controlled by the memory controller would be motivated to use the memory controller as the semiconductor device and the memory device as the upper semiconductor device, as taught by Min, in the semiconductor package of Kim in view of Kang to facilitate effective heat dissipation.
Thus, the combination of Kim, Kang, and Min meets all the limitations of claim 19.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0197831 A1) in views of Kang (US 2021/0118765 A1) and Min (US 2016/0276308 A1).
Regarding claim 20, Kim teaches a semiconductor package (semiconductor package, Fig. 9, [0132]-[0133]), comprising:
a lower redistribution structure (second redistribution layer 20b, Figs. 6, [0113], shown as the lower distribution structure in Illustrative Fig. 5 which is an annotated version of Fig. 9);
a semiconductor device (electronic device 1, Fig. 6, [0112], shown as semiconductor device in Illustrative Fig. 5) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 5) and including a logic device ([0145]: “an integrated circuit”; integrated circuits typically perform logic operations, and therefore include logic circuits);
a lower encapsulant (insulating member 49a, Figs. 4, [0114], shown as lower encapsulant in Illustrative Fig. 5) disposed on the lower redistribution structure (lower distribution structure, Illustrative Fig. 5) and surrounding a side surface of the semiconductor device (semiconductor device, Illustrative Fig. 5);
an upper composite redistribution structure (comprising first redistribution layer 20a (Fig. 6, [0116]), labeled as primary conductive structure in Illustrative Fig. 5, and electrical connections (not described by Kim) labeled as secondary conductive structure in Illustrative Fig. 5 ([0133]-[0134])) disposed on the semiconductor device (semiconductor device, Illustrative Fig. 5);
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conductive posts (interlayer connection conductors 48 (Figs. 3 and 9, labeled as conductive posts in Illustrative Fig. 5, [0116]) electrically connecting the upper composite redistribution structure (comprising the primary conductive structure and secondary conductive structure, Illustrative Fig. 5) with the lower redistribution structure (lower distribution structure, Illustrative Fig. 5) and spaced apart from the semiconductor device (semiconductor device, Illustrative Fig. 5); and
an upper semiconductor device (electronic component 300 shown as upper semiconductor device in Illustrative Fig. 5, [0135]: “The electronic component 300 may be an active … device.”) disposed on the upper composite redistribution structure (comprising the primary conductive structure and secondary conductive structure, Illustrative Fig. 5),
wherein the upper composite redistribution structure (comprising the primary conductive structure and secondary conductive structure, Illustrative Fig. 5) comprises:
a primary conductive structure (primary conductive structure, Illustrative Fig. 5);
a secondary conductive structure (secondary conductive structure, Illustrative Fig. 5) disposed on an upper portion of the primary conductive structure (primary conductive structure, Illustrative Fig. 5);
connection vias (connection vias, Illustrative Fig. 5) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 5) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 5);
a heat dissipation plate (heat dissipating conductor 48a labeled as heat dissipation plate in Illustrative Fig. 5, [0077]-[0078]) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 5) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 5) and laterally spaced apart from the connection vias (connection vias, Illustrative Fig. 5) ;
an upper encapsulant (first insulating protective layer 30a, Fig. 6, [0117], shown as upper encapsulant in Illustrative Fig. 5) disposed between the primary conductive structure (primary conductive structure, Illustrative Fig. 5) and the secondary conductive structure (secondary conductive structure, Illustrative Fig. 5) and surrounding the connection vias (connection vias, Illustrative Fig. 5) and a side surface of the heat dissipation plate (heat dissipation plate, Illustrative Fig. 5);
first heat dissipation vias (via connections attached to the heat dissipation plate, see first heat dissipation vias in Illustrative Fig. 5) passing through the primary conductive structure (primary conductive structure, Illustrative Fig. 5), and having one end (bottom end)) contacting a top surface of the semiconductor device (semiconductor device, Illustrative Fig. 5) and the other end (top end) contacting the heat dissipation plate (heat dissipation plate, Illustrative Fig. 5).
Kim, however, does not teach that
upper semiconductor device includes a memory device;
second heat dissipation vias passing through the secondary conductive structure and having one end contacting the heat dissipation plate;
a connection pad electrically connected to each of the connection vias and disposed on the secondary conductive structure; and
a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface contacting the other end of each of the second heat dissipation vias.
Kang, on the other hand, also teaches a semiconductor package (semiconductor package 100H, Fig. 21, [0090]), comprising a lower redistribution structure (backside wiring layer 132, Fig. 21, [0025]), a semiconductor device (second semiconductor chip 122, Fig. 21, [022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21), a lower encapsulant (first encapsulant 131, Fig. 21, [0022]) disposed on the lower redistribution structure (backside wiring layer 132, Fig. 21) and surrounding a side surface of the semiconductor device (both left and right side-surfaces of second semiconductor chip 122, Fig. 21), an upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]) disposed on the semiconductor device (second semiconductor chip 122, Fig. 21), wherein the upper composite redistribution structure (interconnect structure 140, Fig. 21, [0040]: “interconnect structure 140 may include more or fewer of the insulating layers, the redistribution layers, and the redistribution via layers than the example illustrated in the diagram”) comprises a primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21, [0040]), a secondary conductive structure (topmost redistribution layer 142, Fig. 21, [0025]) disposed on an upper portion of the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), connection vias (vias in the top redistribution via layers 143, Fig. 21, [0040]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21), a heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21, [0031]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and laterally spaced apart from the connection vias (vias in the top redistribution via layers 143, Fig. 21), an upper encapsulant (topmost insulating layer 141, Fig. 21, [0057]) disposed between the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21) and the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and surrounding the connection vias (vias in the topmost redistribution via layers 143, Fig. 21) and a side surface of the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21), first heat dissipation vias (heat dissipation via 143HV in the bottommost and middle redistribution via layers 143, Fig. 21, [0044]) passing through the primary conductive structure (comprising bottom and middle redistribution layers 142, and bottom and middle insulating layers 141, Fig. 21), and having one end contacting a top surface of the semiconductor device (second semiconductor chip 122, Fig. 21) and the other end contacting the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21). Kang further teaches
second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21) passing through the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and having one end (bottom end) contacting the heat dissipation plate (heat dissipation pattern 142HP in the middle redistribution layer 142, Fig. 21);
a connection pad (Fig. 21: each connection via has an associated connection pad) electrically connected to each of the connection vias (vias in the top redistribution via layers 143, Fig. 21) and disposed on the secondary conductive structure (topmost redistribution layer 142, Fig. 21); and
a heat dissipation pad (heat dissipation pattern 142HP in the top redistribution layer 142 and heat dissipation member 127, Fig. 21, [0035]) disposed on the secondary conductive structure (topmost redistribution layer 142, Fig. 21) and having a bottom surface contacting the other end (top end) of each of the second heat dissipation vias (heat dissipation via 143HV in the topmost redistribution layer 142, Fig. 21).
Kang further discloses that having the heat dissipation pattern 142 HP and heat dissipation vias 143HV helps to transfer the heat from the semiconductor device to the heat dissipation member 127 ([0045]), and furthermore exposing the heat dissipation member 127 on the upper surface of the package improves heat dissipation efficiency ([0045]-[0046]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package of Kang is analogous to the semiconductor package of Kim, and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Kim to include connection vias through the upper encapsulant layer contacting the heat dissipation plate, and a heat dissipation pad (such as the heat dissipation pattern 142HP and heat dissipation member 127 of Kang) on the secondary conductive structure, as taught by Kang, to improve the efficiency of heat dissipation from the semiconductor device. Thus, the combination of Kim and Kang teaches that the semiconductor package further comprises (see Illustrative Fig. 6 as an illustration of the semiconductor package of Kim modified by Kang)
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second heat dissipation vias passing through the secondary conductive structure and having one end contacting the heat dissipation plate;
a connection pad electrically connected to each of the connection vias and disposed on the secondary conductive structure; and
a heat dissipation pad disposed on the secondary conductive structure and having a bottom surface contacting the other end of each of the second heat dissipation vias.
Kim and Kang, however, do not teach that
upper semiconductor device includes a memory device.
Min, on the other hand, teaches a semiconductor package (package-on-package (POP) structure 300, Fig. 3A, [0071]), which is analogous to the semiconductor package of Kim in view of Kang in that the package comprises a semiconductor device (semiconductor device 115, Fig. 3A, [0044]: “a
memory controller semiconductor device” which is a logic device) that generates heat and an upper second semiconductor device (first semiconductor device 140, Fig. 3A, [0077]), wherein
upper semiconductor device includes a memory device ([0077]: DRAM).
A person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to form a semiconductor device package comprising a memory controller device (logic device) that generates heat and a memory device (DRAM) that is controlled by the memory controller would be motivated to use the memory controller as the semiconductor device and the memory device as the upper semiconductor device, as taught by Min, in the semiconductor package of Kim in view of Kang to facilitate effective heat dissipation.
Thus, the combination of Kim, Kang, and Min meets all the limitations of claim 20.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding the closest prior art that can modify the semiconductor package of Kim in view of Kang as applied to claim 6 further towards the invention disclosed in claim 7 is Min (US 2016/0276308 A1). Min teaches embodiments of semiconductor packages with heat dissipation capabilities (see embodiment 1 in Fig. 1A-B ([0043]) and embodiment 2 in Fig. 2A-B ([0057])), which are analogous to the semiconductor package of Kim in view of Kang in that the package comprises a semiconductor device (semiconductor device 115, Figs. 1A and 2A, [0044]) that generates heat, an upper second semiconductor device (first semiconductor device 140, Figs. 1A and 2A, [0077]) and heat dissipating vias (thermal vias 130, Figs. 1A and 2A, [0054]). Min further teaches that that the heat dissipating vias (thermal vias 180, Fig. 1A, [0054]) in the intermediate layers of the semiconductor package (embodiment 1 in Fig. 1A) can be alternatively replaced with a heat plate (thermal trenches filled with thermally conductive material, Fig. 2A, [0068]) leading to the embodiment 2 (Fig. 2A). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor package embodiments of Min are analogous to the semiconductor package of Kim in view of Kang, and replacing the thermal vias with a heat plate would increase the heat dissipation. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the vias (the via above the heat dissipation plate in Illustrative Fig. 1) in the intermediate layers Kim in view of Kang with a heat plate (thermal trenches filled with thermally conductive material, Fig. 2A) as in the case of embodiment 2 (Fig. 2A-B). However, such a replacement would be most beneficial if the heat plate is extended through the upper encapsulant to the surface of the sealing portion 5 of the semiconductor package of Kim in view of Kang, as there is no other heat dissipating material in the semiconductor package which is equivalent to the heat slug 230 in the semiconductor package of Kim in view of Kang. Therefore, there is no motivation to set the thickness of the heat plate of the semiconductor device of Kim in view of Kang to be equal to the thickness of the upper encapsulant.
Therefore, claim 7, disclosing “a thickness of the upper encapsulant in a vertical direction is equal to a thickness of the heat dissipation plate in the vertical direction”, would be allowable if the thickness relationship is written in an independent form or incorporated in a claim combining claims 1-3, and 6-7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai (US 2021/0225785 A1) teaches a semiconductor package with redistribution structures and heat dissipation vias, which is relevant to all claims.
Lee (US 2021/0193555 A1) teaches a semiconductor package with redistribution structures and heat dissipation vias and plate, which is relevant to all claims.
Kim (US 2019/0237382 A1) teaches a semiconductor package with redistribution structures and heat dissipation vias and plate, which is relevant to all claims.
Lee (US 2020/0066613 A1) teaches a semiconductor package with redistribution structures and heat dissipation vias and plate, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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