CTNF 18/520,527 CTNF 99372 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-15-03-aia AIA Claim (s) 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shea (PGPub No 20150357448) . Regarding claim 1, Shea teaches a semiconductor device, comprising: a semiconductor substrate including a bipolar junction transistor region; a pedestal dielectric layer in the bipolar junction transistor region and over an upper surface of the semiconductor substrate; a collector layer on the upper surface of the semiconductor substrate and through the pedestal dielectric layer; a base layer on the collector layer and an upper surface of the pedestal dielectric layer, the pedestal dielectric layer extending laterally over the upper surface of the semiconductor substrate from the base layer; and an emitter layer on the base layer (Fig. 1 points to a BiCMOS device structure 10 comprising a substrate 16, a HBT device 14 (bipolar junction transistor region), collector dielectric layers 48 & 50 (pedestal dielectric layer), a collector interface region 54 (collector layer), a base layer 56, and an emitter active region 74 (emitter layer).). Regarding claim 2, Shea teaches wherein the semiconductor substrate includes: a doped sub-collector diffusion region, the collector layer being on the doped sub-collector diffusion region; and a doped collector contact region in the doped sub-collector diffusion region, at least a portion of the pedestal dielectric layer being laterally between the collector layer and the doped collector contact region (Fig. 1 points to a collector active implant region 40 (sub-collector diffusion region) and a collector contact region 46.). Regarding claim 3, Shea teaches wherein the base layer includes a material dissimilar from a material of the collector layer and a material of the emitter layer ([0029-30] point to the collector interface region 54 (collector layer) being formed from silicon, the base layer 56 from silicon germanium, and the emitter active region 74 from polysilicon.). Regarding claim 4, Shea teaches wherein: the material of the base layer includes silicon germanium; the material of the collector layer is silicon; and the material of the emitter layer is silicon ([0029-30] point to the collector interface region 54 (collector layer) being formed from silicon, the base layer 56 from silicon germanium, and the emitter active region 74 from polysilicon.). Regarding claim 5, Shea teaches a raised base layer on the base layer (Fig. 1 points to an emitter interface layer 58.). Regarding claim 6, Shea teaches a base metal-semiconductor compound on the raised base layer; and an emitter metal-semiconductor compound on the emitter layer (Fig. 1 points to base contacts 86 & 88 (base metal-semiconductor compound) and an emitter contact 80 (emitter metal-semiconductor compound).). Regarding claim 7, Shea teaches a base metal-semiconductor compound on the base layer; and an emitter metal-semiconductor compound on the emitter layer (Fig. 1 points to base contacts 86 & 88 (base metal-semiconductor compound) and an emitter contact 80 (emitter metal-semiconductor compound).) . Claim Rejections - 35 USC § 103 07-21-aia AIA Claim (s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shea (PGPub No 20150357448) in further view of Chen (PGPub No. 20170098665) . Regarding claim 8, Shea teaches wherein: the semiconductor substrate further includes a complementary field effect transistor (CFET) region (Fig. 1 points to a CMOS 12.) Shea fails to teach the CFET region including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET); and a region laterally between the CFET region and a sidewall of the pedestal dielectric layer is exclusive of a material of a gate electrode of the PFET or a gate electrode of the NFET above the upper surface of the semiconductor substrate. Chen teaches the CFET region including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET); and a region laterally between the CFET region and a sidewall of the pedestal dielectric layer is exclusive of a material of a gate electrode of the PFET or a gate electrode of the NFET above the upper surface of the semiconductor substrate (Fig. 18 and [0055] point to a structure 15 (CFET region) comprising fins 44 (NFET) and fins 46 (PFET).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Shea and Chen, such that the CFET region includes a PFET and a NFET in order to improve carrier mobility, said region also creating an exclusive area between the pedestal dielectric layer and a PFET/NFET gate electrode in order to avoid interference between the CFET region and the bipolar junction transistor region . 07-21-aia AIA Claim (s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shea et al. in further view of Kuo (WO 2018004527) . Regarding claim 9, Kuo teaches wherein: a thickness of the collector layer does not exceed 200 nm; and a thickness of the base layer does not exceed 100 nm (Pg. 8, line 33 – Pg. 9, line 2 and Pg. 9, lines 14-17 point to a collector layer 232 with a thickness T4 and a base layer 234 with a thickness T5, said thicknesses both ranging from 10 to 50 nm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim , 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff , 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shea et al. and Kuo, such that the thicknesses of the collector layer and the base layer do not exceed 200 nm and 100 nm respectively in order to increase speeds and lower resistance. Regarding claim 10, Kuo teaches wherein: the thickness of the collector layer is in a range from 10 nm to 100 nm; and the thickness of the base layer is in a range from 10 nm to 50 nm (Pg. 8, line 33 – Pg. 9, line 2 and Pg. 9, lines 14-17 point to a collector layer 232 with a thickness T4 and a base layer 234 with a thickness T5, said thicknesses both ranging from 10 to 50 nm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim , 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff , 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shea et al. and Kuo, such that the thickness of the collector layer is in a range from 10 nm to 100 nm and the thickness of the base layer is in a range from 10 nm to 50 nm in order to better optimize the device for a specific application by balancing properties such as speed, resistance, current capability, and/or breakdown voltage. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/520,527 Page 2 Art Unit: 2899 Application/Control Number: 18/520,527 Page 3 Art Unit: 2899 Application/Control Number: 18/520,527 Page 4 Art Unit: 2899 Application/Control Number: 18/520,527 Page 5 Art Unit: 2899 Application/Control Number: 18/520,527 Page 6 Art Unit: 2899
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