DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/28/2023 and 05/08/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-11, 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 20240332459 A1).
Re: Claim 10, Choi discloses a display device (reproduced Fig. 14 below,), comprising:
PNG
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628
631
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Greyscale
a plurality of light emitting elements (LD); and
an array substrate (SUB), wherein the light emitting elements are disposed on the array substrate, and the array substrate comprises:
a substrate (SUB);
a plurality of switch elements (T), disposed on the substrate;
an insulating layer (GI1, GI2, ILD), disposed on the switch elements and having a plurality of through holes (TH1);
a connecting layer (ACL), disposed on the insulating layer and electrically connected to the switch elements through the through holes;
a conductive layer (EL3), disposed on the connecting layer and comprising a plurality of pads (EL1, EL2) connected to the connecting layer, wherein the light emitting elements are electrically connected to the pads to electrically connect to the switch elements;
a spacer layer (VIA3), disposed between the connecting layer and the conductive layer, wherein the conductive layer extends on the spacer layer, the conductive layer is orthographically projected on the substrate to form a first orthographic projection area and each of the light emitting elements are orthographically projected on the substrate to form a second orthographic projection area wherein the through holes are located in the first orthographic projection area and not located in the second orthographic projection areas.
Re: Claim 11, Choi discloses the display device of claim 10. Choi further discloses the spacer layer comprises an organic insulating layer (¶ [0128]).
Re: Claim 1, Choi discloses a display device (reproduced Fig. 14 above), comprising: a plurality of light emitting elements (LD); and
an array substrate (SUB), wherein the light emitting elements are disposed on the array substrate, and the array substrate comprises:
a substrate (SUB);
a plurality of switch elements (T), disposed on the substrate, wherein each of the switch elements comprises a source electrode (TE1) and a drain electrode (TE2);
a first insulating layer (GI1, GI2, ILD), disposed on the source electrodes and the drain electrodes, and having a plurality of first through holes (TH1);
a wiring layer (CCE), disposed on the first insulating layer and connected to the switch elements through the first through holes;
a second insulating layer (VIA1, PAS1), disposed on the wiring layer and having a plurality of second through holes (TH2);
a connecting layer (ACL), disposed on the second insulating layer and connected to the wiring layer through the second through holes);
a third insulating layer (VIA2, PAS2), disposed on the connecting layer and having a plurality of third through holes (TH3);
a conductive layer (EL3), disposed on the third insulating layer and comprising a plurality of pads (EL1, EL2) connected to the connecting layer through the third through holes;
a spacer layer (VIA3), disposed between the third insulating layer and the conductive layer, wherein the conductive layer extends on the spacer layer, and the conductive layer is orthographically projected on the substrate to form a first orthographic projection area wherein the second through holes are located in the first orthographic projection area.
an upper insulating layer (encapsulation CVL, [0070]), disposed on the pads and having a plurality of connecting vias (EL1, EL2), wherein the light emitting elements are disposed on the upper insulating layer and electrically connected to the pads (EP1, EP2) through the connecting vias EL1, EL2) and the light emitting elements are electrically connected to the switch elements (¶ [0067-68], connection via pixel circuit layer);
Re: Claim 2, Choi discloses (reproduced Fig. 14 above) the display of claim 1and each of the light emitting elements are orthographically projected on the substrate to form a second orthographic projection area wherein the second through holes are not located in the second orthographic projection areas.
Re: Claim 3, Choi discloses (reproduced Fig. 14 above) the display of claim 1 and the first through holes are located in the first orthographic projection area.
Re: Claim 4, Choi discloses (reproduced Fig. 14 above) the display of claim 3 and each of the light emitting elements are orthographically projected on the substrate to form a second orthographic projection area (LD projection area), wherein the first through holes are not located in the second orthographic projection areas.
Re: Claim 5, Choi discloses the display of claim 1. Choi further discloses the spacer layer comprises an organic insulating layer (VIA3 is organic, ¶ [0128]).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 12-14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Choi (US 20240332459 A1) in view of Wang (US 20140268780 A1).
Re: Claim 6, Choi discloses the display of claim 1. Choi does not disclose the conductive layer comprises a plurality of extending part not connected to the connecting layer and separated from the pads.
Wang discloses a light emitting diode interconnection assembly (Figs. 1-8) wherein the conductive layer (20) further comprises a plurality of extending parts (island 26) not connected to the connecting layer and separated from the pads. Wang teaches that such a configuration is to evacuate thermal energy (¶ [0022]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the conductive layer of Choi with the partitioned conductors of Wang to evacuate thermal energy induced in the assembly package.
Re: Claim 7, Choi discloses the display of claim 1. Choi does not disclose the array substrate comprising a protective layer between the spacer layer and the conductive layer, and the conductive layer is not directly in contact with the spacer layer.
Wang further discloses a light emitting diode interconnection assembly (Figs. 3-8) wherein the array substrate further comprises a protective layer (adhesive layer 35) disposed between the spacer layer (75) and the conductive layer (20), and the conductive layer is not directly in contact with the spacer layer. Adding the protective layer (adhesive layer) to isolate other layers is predictable, such that ordinarily skilled artisans would have applied this teaching to separate the two conductive layer and the spacer layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the invention to add a protective layer between the conductive layer and a spacer layer for the isolation purpose as disclosed in Wang to the display of Choi to achieve the same thing.
Re: Claim 8, Choi discloses the display of claim 1. Choi does not disclose the spacer layer has a sidewall located on the third insulating layer, and the protective layer is disposed on the spacer layer and covers the sidewall of the spacer layer.
Wang discloses (Figs. 3-8) the spacer layer (75) has a sidewall (sidewall 75) located on the third insulating layer (30), and the protective layer (35) is disposed on the spacer layer and covers the sidewall of the spacer layer. One of ordinary skill in the art would have adopted the teaching of having the protective layer isolating the spacer sidewall and the third insulating layer. Hence, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to have adopted the protective layer to cover the spacer layer from the conductive layer taught by Wang to the display structure of Choi to achieve thermal energy evacuation.
Re: Claim 12, Choi discloses the display device of claim 10. Choi is silent to the conductive layer further comprises a plurality of extending part not connected to the connecting layer and separated from the pads.
Wang discloses a light emitting diode interconnection assembly (Figs. 1-8) wherein conductive (20) is separated by parts by adhesive layer (35) to evacuate thermal energy. One of ordinary skill would apply the teaching of Wang to separate the conductive layer into different portions, isolated from each other to evacuate thermal energy. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the conductive layer of Choi with the partitioned conductors of Wang to evacuate thermal energy induced in the assembly package.
Re: Claim 13, Choi discloses the display device of claim 10. Choi is silent to the array substrate further comprises a protective layer disposed between the spacer layer and the conductive layer, and the conductive layer is not directly in contact with the spacer layer
Wang further discloses a light emitting diode interconnection assembly (Figs. 1-8) wherein the array substrate further comprises a protective layer (adhesive layer 35) disposed between the spacer layer (75) and the conductive layer (20), and the conductive layer is not directly in contact with the spacer layer. Adding the protective layer (adhesive layer) to isolate other layers is predictable, such that ordinarily skilled artisans would have applied this teaching to separate the two conductive layer and the spacer layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the invention to add a protective layer between the conductive layer and a spacer layer for the isolation purpose as disclosed in Wang to the display of Choi to achieve the same thing.
Re: Claim 14, Choi discloses the display of claim 13. Choi does not disclose the spacer layer has a sidewall located in the insulating layer and the protective layer is disposed on the spacer layer and covers the sidewall of the spacer layer.
Wang discloses (Figs. 3-8) the spacer layer has a sidewall (sidewall 75) located on the insulating layer (30), and the protective layer (35) is disposed on the spacer layer and covers the sidewall of the spacer layer. One of ordinary skill in the art would have adopted the teaching of having the protective layer isolating the spacer sidewall and the third insulating layer. This is predictable to insert a protective layer to cover one layer structure from the other. Hence, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to have adopted the protective layer to cover the spacer layer from the conductive layer taught by Wang to the display structure of Choi to achieve the layer isolation.
Claims 9,15 is rejected under 35 U.S.C. 103 s being patentable by Choi (US 20240332459 A1).
Regarding claim 9, Choi discloses the display of claim 1. Choi further discloses wherein at least one of the first insulating layer (inorganic, (¶ [0122]) and the second insulating layer (inorganic or organic, (¶ [0124]) comprises an organic sub-layer or an inorganic sub-layer. While Choi is silent to the first and/or second insulating layers having an inorganic sub-layer disposed on the organic sub-layer stack, Choi discloses both organic and inorganic layers to be suitable as such to avoid duplicating plurality, less unexpected results. Therefore, it is not inventive to one of ordinary skill in the art to duplicate from among a finite number of possibilities as disclosed (¶ [0124]).
Thus, one of ordinary skill in the art before the effective filing date of the invention would have made such a combination of inorganic and organic sublayers for the first insulating layer as a matter of routine optimization.
Regarding claim 15, Choi discloses the display of claim 1.
Choi further discloses wherein at least one of the first insulating layer (inorganic, (¶ [0122]) and the second insulating layer (inorganic or organic, (¶ [0124]) comprises an organic sub-layer or an inorganic sub-layer. While Choi is silent to the first and/or second insulating layers having an inorganic sub-layer disposed on the organic sub-layer stack, Choi discloses both organic and inorganic layers to be suitable as such to avoid duplicating plurality, less unexpected results. Therefore, it is not inventive to one of ordinary skill in the art to duplicate from among a finite number of possibilities as disclosed (¶ [0124]).
Thus, one of ordinary skill in the art before the effective filing date of the invention would have made such a combination of inorganic and organic sublayers for the first insulating layer as a matter of routine optimization.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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