CTFR 18/520,606 CTFR 91257 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Acknowledgement This office action is in response to the communication filed on 04/15/2026. Claims 1-20 are currently pending in the present application. The amendments to the title and claims 3, 10 and 8-20 have overcome the objection to the specification and claim rejections under 112(b). Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Objections 07-29-01 AIA Claim (s) 2, is/are objected to because of the following informalities: Claim 2 recites “wherein the dielectric liner is disposed along sidewalls a portion of the placeholder ”, which should read “wherein the dielectric liner is disposed along sidewalls of a portion of the placeholder ” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 4, 7, 8, 11, 14, 15, 17, 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jain et al. (US 20230268389 A1; hereinafter “Jain”) . In re claim 1, Jain discloses in figs. 20A-20D in an upside-down view, a semiconductor structure comprising: a nanosheet transistor device comprising a backside source drain contact 258 (¶98), wherein the backside source drain contact 258 comprises a top portion (e.g., a top portion has been interpreted as a portion of the backside source drain contact 258 that is in direct contact with the source/drain epitaxy 236. Hereinafter “ Top_BC ”), a middle portion (“Middle_BC”) , and a bottom portion (“Bottom_BC”) (¶96); and a dielectric liner 226 (a layer of the multi-layer spacer layer 226, that is in contact with the ILD layer 254; ¶77. Hereinafter “ Liner ”) disposed along and directly contacting sidewalls of the top portion of the backside source drain contact ( Top_BC ), wherein a topmost surface of the backside source drain contact 258 is entirely above a topmost surface of the dielectric liner 226 (fig. 20C in an upside-down view), and wherein a bottommost surface of the dielectric liner 226 is entirely above the bottommost surface of the backside source drain contact 258 (see fig. 20C annotated below). PNG media_image1.png 751 900 media_image1.png Greyscale In re claim 4, Jain discloses in figs. 20A-20D in an upside-down view, the semiconductor structure according to claim 1, further comprising: stack spacers 226 (a layer of the multi-layer spacer layer 226, that is not in contact with the ILD layer 254; ¶77. Hereinafter “ Stack_Sp ”) arranged directly beneath nanosheet stacks 212 (¶72) of the nanosheet transistor device, wherein a width of the stack spacers 226 is substantially equal to a width of each of the nanosheet stacks 212 , and wherein the dielectric liner (Liner) is arranged between and physically separates the stack spacers ( Stack_Sp) from a backside dielectric layer 254 . In re claim 7, Jain discloses in figs. 20A-20D in an upside-down view, the semiconductor structure according to claim 1, wherein first opposite sidewalls of the backside source drain contact 258 directly contact adjacent shallow trench isolation regions 216 (fig. 20A; ¶74), and second opposite sidewalls of the backside source drain contact directly 258 contact a backside dielectric layer 254 (fig. 20A; ¶93). In re claim 8, same as claim 1 above. In re claim 11, same as claim 4 above. In re claim 14, same as claim 7 above. In re claim 15, Jain discloses in figs. 20A-20D in an upside-down view, a semiconductor structure comprising: a nanosheet transistor device comprising a backside source drain contact 258 (¶98), wherein the backside source drain contact 258 comprises a top portion (e.g., a top portion has been interpreted as a portion of the backside source drain contact 258 that is in direct contact with the source/drain epitaxy 236. Hereinafter “ Top_BC ”) having a first width (e.g., W1 ), a middle portion (“Middle_BC”) having a second width (e.g., W2 ), a bottom portion (“Bottom_BC”) (¶96) having a third width (e.g., W3 ); wherein the first width of the top portion W1 is substantially equal to a width of the source drain region 236 , wherein the second width of the middle portion W2 is greater than the first width of the top portion W1 , and wherein the third width of the bottom portion W3 is greater than the second width of the middle portion W2 ; and a dielectric liner (a layer of the multi-layer spacer layer 226, that is in contact with the ILD layer 254; ¶77. Hereinafter “ Liner ”) disposed along sidewalls of the first top portion of the backside source drain contact ( Top_BC ). PNG media_image1.png 751 900 media_image1.png Greyscale In re claim 17, same as claim 4 above. In re claim 20, same as claim 7 above . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2, 9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain and further in view of Yun et al. (US 20240395900 A1; hereinafter “Yun”) and D’silva et al. (US 20240332175 A1; hereinafter “D’silva”) . In re claim 2, Jain discloses the semiconductor structure according to claim 1. Jain does not expressly disclose the semiconductor structure further comprising: a placeholder adjacent to the backside source drain contact and directly beneath a source drain region, wherein the dielectric liner is disposed along sidewalls a portion of the placeholder, and wherein a width of the placeholder is substantially equal to a width of the source drain region. In the same field of endeavor, Yun discloses in fig. 3, a semiconductor structure comprising: a placeholder P4 adjacent to the backside source drain contact BC2 and directly beneath a source drain region SD4 (¶42), wherein the dielectric liner 102, 103A is disposed along sidewalls a portion of the placeholder P4 (¶44). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yun into the device of Jain in order to utilize the placeholder to form backside source/drain contact structure in subsequent process steps and maintain isolation between the gate contacts and S/D contacts (¶11-16 of Yun). However, Jian, as modified by Yun, does not expressly disclose wherein a width of the placeholder is substantially equal to a width of the source drain region. In the same field of endeavor, D’silva discloses in fig. 1, a semiconductor structure comprising: a placeholder 122 adjacent to the backside source drain contact 120 and directly beneath a source drain region 110a (¶22), and wherein a width of the placeholder 122 is substantially equal to a width of the source drain region. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of D’silva into the device of Jain/Yun in order to achieve high quality registration of electrical contacts to various structures within the transistor (¶2 of D’silva). In re claims 9 and 16, same as claim 2 above . 07-21-aia AIA Claim (s) 5, 12, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain and further in view of D’silva et al. (US 20240332175 A1; hereinafter “D’silva”) . In re claim 5, Jain discloses the semiconductor structure according to claim 1. Jain does not expressly disclose the device further comprising: a gate having a bottommost surface entirely below a topmost surface of a backside dielectric layer, wherein a sidewall of the dielectric liner directly contacts a sidewall of the gate. In the same field of endeavor, D’silva discloses in fig. 1, a gate 130 having a bottommost surface entirely below a topmost surface of a backside dielectric layer 124 , wherein a sidewall of a dielectric liner 166 directly contacts a sidewall of the gate 130 (¶22). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of D’silva into the device of Jain to have high quality registration of electrical contacts to various structures within the transistor (¶2 of D’silva). In re claims 12 and 18, same as claim 5 above . 07-22-aia AIA Claim (s) 6, 13, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain , as applied to claim 15 above, and further in view of Kim et al. (US 20200373331 A1; hereinafter “Kim”) . In re claim 6, Jain discloses the semiconductor structure according to claim 1 outlined above. Jain does not expressly disclose wherein first sidewalls of the dielectric liner directly contact sidewalls of shallow trench isolation regions, and opposite sidewalls of the backside source drain contact directly contact the sidewalls of the shallow trench isolation regions. In the same field of endeavor, Kim discloses in fig. 21, a semiconductor structure comprising a backside source drain contact (VC, 150, 160) (¶109, 111, 125), a dielectric liner 112c (¶98), shallow trench isolation regions 112b (¶98), wherein first sidewalls of the dielectric liner 112c directly contact sidewalls of shallow trench isolation regions 112b , and opposite sidewalls of the backside source drain contact 150 directly contact the sidewalls of the shallow trench isolation regions 112b . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kim into the semiconductor structure of Jain and arrive at the claimed invention. One would have been motivated to do so as Kim teaches the modern integrated circuit device that is highly integrated has to have a lot of wiring layers arranged within a small area while stably ensuring insulation distances among the wiring layers (¶3-7 of Kim). In re claim 13, same as claim 6 above. In re claim 19, Jain discloses the semiconductor structure according to claim 15 outlined above. Jain does not expressly disclose wherein first sidewalls of the dielectric liner directly contact sidewalls of shallow trench isolation regions, and opposite sidewalls of the backside source drain contact directly contact the sidewalls of the shallow trench isolation regions. In the same field of endeavor, Kim discloses in fig. 21, a semiconductor structure comprising a backside source drain contact (VC, 150, 160) (¶109, 111, 125), a dielectric liner 112c (¶98), shallow trench isolation regions 112b (¶98), wherein first sidewalls of the dielectric liner 112c directly contact sidewalls of shallow trench isolation regions 112b , and opposite sidewalls of the backside source drain contact 150 directly contact the sidewalls of the shallow trench isolation regions 112b . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kim into the semiconductor structure of Jain and arrive at the claimed invention. One would have been motivated to do so as Kim teaches the modern integrated circuit device that is highly integrated has to have a lot of wiring layers arranged within a small area while stably ensuring insulation distances among the wiring layers (¶3-7 of Kim) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3, 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 3, closest prior art of record, alone or in combination, does not expressly disclose a device comprising a buffer layer between and physically separating the placeholder from the source drain region, wherein a width of the buffer layer is substantially equal to a width of the source drain region, in combination with all other limitations of claims 1 and 2. Regarding claim 10, closest prior art of record, alone or in combination, does not expressly disclose a device comprising a buffer layer between and physically separating the placeholder from the source drain region, wherein a width of the buffer layer is substantially equal to a width of the source drain region, in combination with all other limitations of claims 8 and 9. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NILUFA RAHIM/Primary Examiner, Art Unit 2893 Application/Control Number: 18/520,606 Page 2 Art Unit: 2893 Application/Control Number: 18/520,606 Page 3 Art Unit: 2893 Application/Control Number: 18/520,606 Page 4 Art Unit: 2893 Application/Control Number: 18/520,606 Page 5 Art Unit: 2893 Application/Control Number: 18/520,606 Page 6 Art Unit: 2893 Application/Control Number: 18/520,606 Page 7 Art Unit: 2893 Application/Control Number: 18/520,606 Page 8 Art Unit: 2893 Application/Control Number: 18/520,606 Page 9 Art Unit: 2893 Application/Control Number: 18/520,606 Page 10 Art Unit: 2893 Application/Control Number: 18/520,606 Page 11 Art Unit: 2893
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