Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “BACKSIDE DIELECTRIC LINERS FOR NANOSHEET TRANSISTOR STRUCTURES”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, and 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 15 recite the limitation ".. the first portion of the backside source drain contact" in lines 5-6 and 7-8, respectively. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, these limitations will be interpreted as “the top portion of the backside source drain contact”.
Dependent claims 9-14 and 16-20 do not rectify the deficiency and likewise, rejected under this section.
Claim 3 recites “a source drain region” in lines 2-3. This causes ambiguity in the claim as to whether it is referring to the same or a different source drain region cited in lines 2-3 cited in claim 2, upon which claim 3 depends. For the purposes of examination, this will be interpreted as same source drain region. Hence, claim 3 has been treated as “The semiconductor structure according to claim 2, further comprising: a buffer layer between and physically separating the placeholder from the source drain region”.
Claim 10 recites “a source drain region” in lines 2-3. This causes ambiguity in the claim as to whether it is referring to the same or a different source drain region cited in lines 2-3 cited in claim 9, upon which claim 3 depends. For the purposes of examination, this will be interpreted as same source drain region. Hence, claim 3 has been treated as “The semiconductor structure according to claim 2, further comprising: a buffer layer between and physically separating the placeholder from the source drain region”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9, 11-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yun et al. (US 20240395900 A1; hereinafter “Yun”).
In re claim 1, Yun discloses a semiconductor structure 30 (fig. 3) comprising:
a nanosheet transistor device comprising a backside source drain contact BC2 (¶6, 52),
wherein the backside source drain contact BC2 comprises a top portion, a middle portion, and a bottom portion (as shown in 3, the backside source drain contact BC2 has a top portion adjacent to the S/D region SD2, a bottom portion at the bottom of the contact BC2, a middle portion in between the top and bottom portions. These three portions will be labeled as “BC2_top”, “BC2_middle”, “BC2_bottom”); and
a dielectric liner 102, 103A disposed along sidewalls of the top portion of the backside source drain contact (BC2_top) (¶45-46).
In re claim 2, Yun discloses in fig. 3, the semiconductor structure according to claim 1, further comprising: a placeholder P4 adjacent to the backside source drain contact BC2 and directly beneath a source drain region SD4 (¶42), wherein the dielectric liner 102, 103A is disposed along sidewalls a portion of the placeholder P4 (¶44).
In re claim 4, Yun discloses in fig. 3, the semiconductor structure according to claim 1, wherein the dielectric liner 102, 103A further separated a backside dielectric layer 106 from stack spacers 104 arranged directly beneath a nanosheet stacks 110 of the nanosheet transistor device (¶61).
In re claim 5, Yun discloses in fig. 3, the semiconductor structure according to claim 1, wherein the dielectric liner 102, 103A further separates a backside dielectric layer 106 from a gate G4 (¶61).
In re claim 6, Yun discloses in fig. 3, the semiconductor structure according to claim 1, wherein sidewalls of the dielectric liner 102, 103A directly contact sidewalls of shallow trench isolation regions 106 (backside isolation structures 106 have been interpreted as shallow trench isolation regions) (¶77-78).
In re claim 7, Yun discloses in fig. 3, all the limitations of the semiconductor structure according to claim 1 upon which this claim depends. The limitations cited in this claim “wherein the backside source drain contact is self-aligned to shallow trench isolation regions” pertains to be a product-by-process limitation and the process of forming a mark does not distinguish the product from the prior art. Referring to MPEP §2113, regarding Product-by-Process Claims:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).”
“Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)”.
In re claim 8, Yun discloses a semiconductor structure 30 (fig. 3) comprising:
a nanosheet transistor device comprising a backside source drain contact BC2 (¶6, 52),
wherein the backside source drain contact BC2 comprises a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width (as shown in 3, the backside source drain contact BC2 has a top portion adjacent to the S/D region SD2 having a first width, a bottom portion at the bottom of the contact BC2 having a third width, a middle portion in between the top and bottom portions having a second width. These three portions will be labeled as “BC2_top”, “BC2_middle”, “BC2_bottom”); and
a dielectric liner 102, 103A disposed along sidewalls of the first portion of the backside source drain contact (BC2_top) (¶45-46).
In re claim 9, Yun discloses in fig. 3, the semiconductor structure according to claim 8, further comprising: a placeholder P4 adjacent to the backside source drain contact BC2 and directly beneath a source drain region SD4 (¶42), wherein the dielectric liner 102, 103A is disposed along sidewalls a portion of the placeholder P4.
In re claim 11, Yun discloses in fig. 3, the semiconductor structure according to claim 8, wherein the dielectric liner 102, 103A further separated a backside dielectric layer 106 from stack spacers 104 arranged directly beneath a nanosheet stacks 110 of the nanosheet transistor device (¶61).
In re claim 12, Yun discloses in fig. 3, the semiconductor structure according to claim 8, wherein the dielectric liner 102, 103A further separates a backside dielectric layer 106 from a gate G4 (¶61).
In re claim 13, Yun discloses in fig. 3, the semiconductor structure according to claim 8, wherein sidewalls of the dielectric liner 102, 103A directly contact sidewalls of shallow trench isolation regions 106 (backside isolation structures 106 have been interpreted as shallow trench isolation regions) (¶77-78).
In re claim 14, Yun discloses in fig. 3, all the limitations of the semiconductor structure according to claim 8 upon which this claim depends. The limitations cited in this claim “wherein the backside source drain contact is self-aligned to shallow trench isolation regions” pertains to be a product-by-process limitation and the process of forming a mark does not distinguish the product from the prior art. Referring to MPEP §2113, regarding Product-by-Process Claims:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).”
“Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)”.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 20240421154 A1; hereinafter “Lee”).
In re claim 1, Lee discloses in figs. 1-2, a semiconductor structure comprising:
a nanosheet transistor device TS (¶16) comprising a backside source drain contact 222, 218, 220 (¶33-35; here, source drain contact has been interpreted as comprising conductive layers 222, 218 and 220),
wherein the backside source drain contact 222, 218, 220 comprises a top portion (e.g., 222), a middle portion (e.g., 218), and a bottom portion (e.g., 220); and
a dielectric liner 210 (¶28) disposed along sidewalls of the top portion of the backside source drain contact 222.
In re claim 8, Lee discloses in figs. 1-2, a semiconductor structure comprising:
a nanosheet transistor device TS (¶16) comprising a backside source drain contact 222, 218, 220 (¶33-35; here, source drain contact has been interpreted as comprising conductive layers 222, 218 and 220),
wherein the backside source drain contact 222, 218, 220 comprises a top portion having a first width (e.g., 222 having a first width), a middle portion having a second width (e.g., 218 having a second width), and a bottom portion having a third width (e.g., 220 having a third width); and
a dielectric liner 210 (¶28) disposed along sidewalls of the top portion of the backside source drain contact 222.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 20220165856 A1; hereinafter “Yu”).
In re claim 15, Yu discloses a semiconductor structure 200 (fig. 15) comprising:
a nanosheet transistor device 300 comprising source drain region 226S and a backside source drain contact 280 (¶2, 17, 32),
wherein the backside source drain contact 280 comprises a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width (as shown in 15, the backside source drain contact 280 has a top portion adjacent to the S/D region 226S having a first width, a bottom portion at the bottom of the contact 280 having a third width, a middle portion in between the top and bottom portions having a second width. These three portions will be labeled as “280_top”, “280_middle”, “280_bottom”);
wherein the first width of the top portion (280_top) is substantially equal to a width of the source drain region 226S (see fig. 15); and
a dielectric liner 284 disposed along sidewalls of the first portion of the backside source drain contact (280_top) (¶32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to claims 1 and 8 above, respectively and further in view of Yun.
In re claim 2, Lee discloses in figs. 1-2, the semiconductor structure according to claim 1, further comprising:
a placeholder 216a adjacent to the backside source drain contact 222, 218, 220 and directly beneath a source drain region 102b (¶43).
Lee does not expressly disclose wherein the dielectric liner is disposed along sidewalls a portion of the placeholder.
In the same field of endeavor, Yun discloses in fig. 3, a semiconductor structure 30 wherein a dielectric liner 103A is disposed along sidewalls a portion of the placeholder P4 (¶44).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yun into the nanosheet transistor device of Lee and form a dielectric liner along sidewalls a portion of the placeholder to provide an additional or back-up isolation profile to the backside of the semiconductor device (¶46 of Yun).
In re claim 3, Lee, as modified by Yun, discloses the semiconductor structure according to claim 2 outlined above.
Lee further discloses in figs. 1-2, the semiconductor device further comprising:
a buffer layer 222 between and physically separating the placeholder 216a from a source drain region 102b (as best understood, the source drain region).
In re claim 9, Lee discloses in figs. 1-2, the semiconductor structure according to claim 8, further comprising:
a placeholder 216a adjacent to the backside source drain contact 222, 218, 220 and directly beneath a source drain region 102b (¶43).
Lee does not expressly disclose wherein the dielectric liner is disposed along sidewalls a portion of the placeholder.
In the same field of endeavor, Yun discloses in fig. 3, a semiconductor structure 30 wherein a dielectric liner 103A is disposed along sidewalls a portion of the placeholder P4 (¶44).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yun into the nanosheet transistor device of Lee and form a dielectric liner along sidewalls a portion of the placeholder to provide an additional or back-up isolation profile to the backside of the semiconductor device (¶46 of Yun).
In re claim 10, Lee, as modified by Yun, discloses the semiconductor structure according to claim 9 outlined above.
Lee further discloses in figs. 1-2, the semiconductor device further comprising:
a buffer layer 222 between and physically separating the placeholder 216a from a source drain region 102b (as best understood, the source drain region).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Yu et al. (US 20220165856 A1; hereinafter “Yu”).
In re claim 15, Yun discloses a semiconductor structure 30 (fig. 3) comprising:
a nanosheet transistor device comprising source drain region SD2 and a backside source drain contact BC2 (¶6, 40, 52),
wherein the backside source drain contact BC2 comprises a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width (as shown in 3, the backside source drain contact BC2 has a top portion adjacent to the S/D region SD2 having a first width, a bottom portion at the bottom of the contact BC2 having a third width, a middle portion in between the top and bottom portions having a second width. These three portions will be labeled as “BC2_top”, “BC2_middle”, “BC2_bottom”); and
a dielectric liner 102, 103A disposed along sidewalls of the first portion of the backside source drain contact (BC2_top) (as best understood, the first portion of the backside source drain contact has been understood as the top portion of the backside source drain contact) (¶45-46).
Yun does not expressly disclose wherein the first width of the top portion is substantially equal to a width of the source drain region.
In the same field of endeavor, Yu discloses a semiconductor structure 200 (fig. 15), wherein the first width of the top portion (as shown in 15, the backside source drain contact 280 has a top portion adjacent to the S/D region 226S) is substantially equal to a width of the source drain region 226S (¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yu into the device of Yun and make the top portion of the backside source drain contact having a width that is substantially equal to a width of the source drain region in order to enhance the surface area of contact region to the source drain region and reduce contact resistance.
In re claim 16, Yun, as modified by Yu, discloses the semiconductor structure according to claim 15.
Yun further discloses in fig. 3, the semiconductor structure according to claim 15, further comprising: a placeholder P4 adjacent to the backside source drain contact BC2 and directly beneath a source drain region SD4 (¶42), wherein the dielectric liner 102, 103A is disposed along sidewalls a portion of the placeholder P4.
In re claim 17, Yun, as modified by Yu, discloses the semiconductor structure according to claim 15.
Yun further discloses in fig. 3, the semiconductor structure according to claim 15, wherein the dielectric liner 102, 103A further separated a backside dielectric layer 106 from stack spacers 104 arranged directly beneath a nanosheet stacks 110 of the nanosheet transistor device (¶61).
In re claim 18, Yun, as modified by Yu, discloses the semiconductor structure according to claim 15.
Yun further discloses in fig. 3, the semiconductor structure according to claim 15, wherein the dielectric liner 102, 103A further separates a backside dielectric layer 106 from a gate G4 (¶61).
In re claim 19, Yun, as modified by Yu, discloses the semiconductor structure according to claim 15.
Yun further discloses in fig. 3, the semiconductor structure according to claim 151111, wherein sidewalls of the dielectric liner 102, 103A directly contact sidewalls of shallow trench isolation regions 106 (backside isolation structures 106 have been interpreted as shallow trench isolation regions) (¶77-78).
In re claim 20, Yun, as modified by Yu, discloses all the limitations of the semiconductor structure according to claim 15 upon which this claim depends. The limitations cited in this claim “wherein the backside source drain contact is self-aligned to shallow trench isolation regions” pertains to be a product-by-process limitation and the process of forming a mark does not distinguish the product from the prior art. Referring to MPEP §2113, regarding Product-by-Process Claims:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).”
“Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893