Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-5, in the “Response to Election / Restriction Filed - 03/02/2026”, withdrawal of non-elected claim(s) 6-9 is/are acknowledged. This office action considers claims 1-9, in “Claims - 03/02/2026”, pending for prosecution, of which claim(s) 6-9 is/are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kadoguchi et al. (US 20140035112 A1 – hereinafter Kadoguchi).
Regarding Claim 1, Kadoguchi teaches a semiconductor device (see the entire document; Fig. 6C; specifically, ([0112] - [0116]), and as cited below), comprising:
a first connection target (10 – Fig. 6C – [0113]) and a second connection target (20) arranged on one surface of a substrate ({31, 32});
a first lead wire ({12, 12a, 14}) connected to the first connection target (10);
a second lead wire ({22, 22a, 24}) connected to the second connection target (20); and
a sealing resin (53 – [0116]) that seals the first connection target (10), the second connection target (20), the first lead wire ({12, 12a, 14, 14a}), and the second lead wire ({22, 22a, 24, 24a}), wherein
the first lead wire ({12, 12a, 14, 14a}) includes
a first connection portion (12) connected to the first connection target (10),
a first top portion (14a) exposed from the sealing resin (53), and
a first standing portion (14) inclined with respect to the one surface and connecting the first connection portion (12) and the first top portion (14a),
the second lead wire ({22, 22a, 24}) includes
a second connection portion (22) connected to the second connection target (20),
a second top portion (24a) exposed from the sealing resin (53), and
a second standing portion (24) inclined with respect to the one surface and connecting the second connection portion (22) and the second top portion (24a), and
the first top portion (14a) and the second top portion (14a) are disposed to face each other (they face laterally).
Regarding Claim 2, Kadoguchi teaches the semiconductor device according to claim 1, wherein the first top portion and the second top portion face each other across a recess formed in the sealing resin (recess being where 43 and 33 are formed).
Regarding Claim 3, Kadoguchi teaches the semiconductor device according to claim 2, wherein an end surface of the first top portion (top end) and an end surface of the second top portion (top end) are exposed from the sealing resin (53) in the recess.
Regarding Claim 4, Kadoguchi teaches the semiconductor device according to claim 2, further comprising an embedded resin embedding the recess (Fig. 6C shows the recess is embedded by resin 53).
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5: The semiconductor device according to claim 1, wherein the first top portion has a tapered shape in which a thickness decreases from a part connected to the first standing portion toward an end part facing the second top portion, and the second top portion has a tapered shape in which a thickness decreases from a part connected to the second standing portion toward an end part facing the first top portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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