DETAILED ACTION
Response to Arguments
Applicant's arguments filed 04/28/2026 have been fully considered but they are not persuasive. In regard to claim 1 and claim 12 applicant argues that Kim et al. (US 2020/0303479 A1) fails to teach the following:
“each of the first portion of the organic material layer and groove has a length in the second direction, a width in the first direction, and a depth in a third direction perpendicular to both the first direction and the second direction, each of the second portion of the organic material layer and the wiring line has a length in the extension direction of the wiring line, a width in a direction perpendicular to the extension direction of the wiring line, and a depth in the third direction ,the width of the first portion of the organic material layer is greater than a width of the groove, and the width of the second portion of the organic material layer is greater than the width of the wiring line”.
The examiner respectfully disagrees. The Applicant asserts that the amended limitation is not taught since “Kim merely discloses an organic filler 161 overlapping a groove GR, but fails to disclose a second portion protruding from the first portion in the extension direction of the wiring line and overlapping the wiring line. Specifically, the organic filler 161 of Kim corresponds only to the first portion of the organic material layer (which overlaps the groove and has a width greater than the groove's width)”. The Examiner respectfully disagrees with this assertion as Kim teaches that the organic filler 161 has convex shape and sloped such that there exist an angle of 45° between the upper surface organic filler and the upper surface of the inorganic insulating (paragraphs 142-143). This would mean that the depiction of the organic filler 161 as shown in Fig. 5A is an accurate depiction in shape and layout. Therefore, as shown in Fig. 5A, the shape of the organic layer 161 shows that there would be an inner and an outer portion of the organic layer 161 that extends past the groove as shown in annotated Fig. 5 below. The inner portion extends over the edge of the groove, while the outer portion is the remaining portion of the organic layer 161 outside the groove in the lateral direction. Further, as the groove itself is sloped as taught by Kim, the upper portion of the organic layer 161 would be wider than the lower portion of the groove. Also, as shown in Fig. 4, the organic layer 161 has a width in a direction perpendicular to the extension direction of the wiring line, which is the second direction.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-8 and 12-14 and 16-18 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 2020/0303479 A1; hereinafter “Kim”).
In regard to claim 1, Kim teaches a display apparatus (a display apparatus as shown in Fig. 1) (Fig. 1 and paragraph 29) comprising:
a substrate (a substrate 100) including a plurality of sub-pixel areas (areas containing pixels PX1, PX2, and PX3) (Fig. 5A and paragraphs 87);
an inorganic insulating layer (the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES are collectively referred to as the inorganic material layer) defining a groove between two adjacent sub-pixel areas from among the plurality of sub-pixel areas in a plan view (the groove GR is in an area between a first pixel PX1 and a second pixel PX2) (Fig. 5A and paragraph 87);
an organic material layer filled in the groove (an organic filler 161 is shown in the groove GR in Fig. 5A) (Fig. 5A and paragraph 95); and
a wiring line (a first connection wiring 140) disposed on the organic material layer and passing through the two adjacent sub-pixel areas in a first direction (the first connection wiring 140 is shown between pixels PX1 and PX2 in a first direction and on the organic filler 161 in Fig. 5A),
wherein the organic material layer includes a first portion (the inner portion of the organic filler 161 that extends over the third gate insulating layer 114 annotated as FP as shown in annotated Fig. 5A below) overlapping the groove and extending in a second direction perpendicular to the first direction in the plan view and a second portion (the outer portions of the organic filler 161 that extends over the third gate insulating layer 114 annotated as SP as shown in annotated Fig. 5A below) protruding from the first portion in an extension direction (first direction) of the wiring line and overlapping the wiring line (the portion of the organic filler 161 annotated as FP is shown overlapping the groove and extending in a second direction perpendicular to the first direction in Fig. 4, the outer portions of the organic filler 161 annotated as SP is shown in the second direction and overlapping with the wiring line in Fig. 5A) (Fig. 4, Fig. 5A and paragraphs 142-143),
each of the first portion of the organic material layer and groove has a length in the second direction, a width in the first direction, and a depth in a third direction perpendicular to both the first direction and the second direction (the groove GR and the inner portion of the organic filler 161 that extends over the third gate insulating layer 114 are shown having a length in the second direction, a width in the first direction and a depth in a third direction is shown in Fig. 4 and Fig. 5) (Fig. 4, Fig. 5 and paragraphs 142-143),
each of the second portion of the organic material layer and the wiring line has a length in the extension direction of the wiring line, a width in a direction perpendicular to the extension direction of the wiring line, and a depth in the third direction (the outer portion of the organic filler 161 that extends over the third gate insulating layer 114 are shown having a length in the second direction, a width in the first direction and a depth in a third direction is shown in Fig. 4 and Fig. 5) (Fig. 4, Fig. 5A and paragraphs 142-143),
the width of the first portion of the organic material layer is greater than a width of the groove (as the groove GR is sloped within a range of 10° to 45°, the inner and outer portions of the organic filler 161 that extend laterally over the third gate insulating layer 114 would have a width greater than the groove GR as shown in Fig. 5A) (Fig. 5A and paragraphs 142-143), and
the width of the second portion of the organic material layer is greater than the width of the wiring line (the width of the first connection wiring 140 is in the second direction as it is perpendicular to the extension or first direction of the first connection wiring 140, Fig. 4 shows the organic filler 161 has a greater width in the second direction than the first connection wiring 140).
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In regard to claim 2, Kim teaches wherein the second portion of the organic material layer is disposed under the wiring line (the portion of the organic filler 161 overlapping the groove GR is shown under the first connection wiring 140 in Fig. 5A).
In regard to claim 4, Kim teaches wherein a vertical distance from an upper surface of the substrate to an upper surface of the organic material layer is greater than a vertical distance from the upper surface of the substrate to an upper surface of the inorganic insulating layer (the top surface of the organic filler 161 is shown above the third gate insulating layer 114 as shown in Fig. 5A).
In regard to claim 5, Kim teaches the wiring line is in direct contact with the organic material layer (the organic filler 161 is shown contacting the first connection wiring 140 in Fig. 5A).
In regard to claim 6, Kim teaches wherein the groove surrounds at least some of the plurality of sub-pixel areas in the plan view (the groove GR is shown surrounding the pixels in Fig. 4) (Fig. 4).
In regard to claim 7, Kim teaches wherein the groove surrounds each of the plurality of sub-pixel areas in the plan view (the groove GR is shown surrounding the pixels in Fig. 4) (Fig. 4).
In regard to claim 8, Kim teaches a first thin-film transistor (a thin film transistor T1) disposed in each of the plurality of sub-pixel areas and including a first semiconductor layer (a driving channel area A1 is a driving semiconductor layer) and a first gate electrode (a driving gate electrode G1) overlapping a channel region of the first semiconductor layer (the driving gate electrode G1 is arranged to overlap the driving channel area A1 in a driving semiconductor layer) (Fig. 5A and paragraph 112); and
an electrode (a second electrode Cst2) overlapping and electrically connected to one of a source region (a driving source electrode S1) and a drain region (a driving drain electrode D1) of the first semiconductor layer in the plan view (the second electrode Cst2 overlaps the driving source electrode S1 and is electrically connected to the driving source electrode S1 through the driving voltage line 152) (Fig. 3, Fig. 5A and paragraphs 69 and 125).
In regard to claim 12, Kim teaches display apparatus (a display apparatus as shown in Fig. 1) (Fig. 1 and paragraph 29), comprising:
a substrate (a substrate 100) including a first sub-pixel area (areas containing pixels PX1) and a second sub-pixel area (areas containing pixels PX2) adjacent to each other (areas containing pixels PX1 and PX2 are shown adjacent to each other in Fig. 5A) (Fig. 5A and paragraphs 87);
a first thin-film transistor (a driving thin film transistor T1 under PX1) disposed in the first sub-pixel area and including a first semiconductor layer (a driving channel area A1 under PX1 is a driving semiconductor layer) and a first gate electrode (a driving gate electrode G1 under PX1) (Fig. 5A and paragraph 112);
a second thin-film transistor (a driving thin film transistor T1 under PX2) disposed in the second sub-pixel area and including a second semiconductor layer (a driving channel area A1 under PX2 is a driving semiconductor layer) and a second gate electrode (a driving gate electrode G1 under PX2) (Fig. 5A and paragraph 112);
an inorganic insulating layer (the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES are collectively referred to as the inorganic material layer) defining a groove (a groove GR) between the first sub-pixel area and the second sub-pixel area in a plan view (the groove GR is in an area between a first pixel PX1 and a second pixel PX2 in the first direction) (Fig. 5A and paragraph 87);
an organic material layer filed in the groove (an organic filler 161 is shown in the groove GR in Fig. 5A) (Fig. 5A and paragraph 95); and
a wiring line (a first connection wiring 140) disposed on the organic material layer and passing through the first sub-pixel area and the second sub-pixel area in a first direction (the first connection wiring 140 is shown between pixels PX1 and PX2 and on the organic filler in a first direction 161 in Fig. 4, and Fig. 5A),
wherein the organic material layer includes a first portion (the inner portion of the organic filler 161 that extends over the third gate insulating layer 114 annotated as FP as shown in annotated Fig. 5A above) overlapping the groove and extending in a second direction perpendicular to the first direction in the plan view and a second portion (the outer portions of the organic filler 161 that extends over the third gate insulating layer 114 annotated as SP as shown in annotated Fig. 5A above) protruding from the first portion in an extension direction (first direction) of the wiring line (the portion of the organic filler 161 annotated as FP is shown overlapping the groove and extending in a second direction perpendicular to the first direction in Fig. 4, the outer portions of the organic filler 161 annotated as SP is shown in the second direction and overlapping with the wiring line in Fig. 5A) (Fig. 4, Fig. 5A and paragraphs 142-143),
each of the first portion of the organic material layer and groove has a length in the second direction, a width in the first direction, and a depth in a third direction perpendicular to both the first direction and the second direction (the groove GR and the inner portion of the organic filler 161 that extends over the third gate insulating layer 114 are shown having a length in the second direction, a width in the first direction and a depth in a third direction is shown in Fig. 4 and Fig. 5) (Fig. 4, Fig. 5 and paragraphs 142-143),
each of the second portion of the organic material layer and the wiring line has a length in the extension direction of the wiring line, a width in a direction perpendicular to the extension direction of the wiring line, and a depth in the third direction (the outer portion of the organic filler 161 that extends over the third gate insulating layer 114 are shown having a length in the second direction, a width in the first direction and a depth in a third direction is shown in Fig. 4 and Fig. 5) (Fig. 4, Fig. 5A and paragraphs 142-143),
the width of the first portion of the organic material layer is greater than a width of the groove (as the groove GR is sloped within a range of 10° to 45°, the inner and outer portions of the organic filler 161 that extend laterally over the third gate insulating layer 114 would have a width greater than the groove GR as shown in Fig. 5A) (Fig. 5A and paragraphs 142-143), and
the width of the second portion of the organic material layer is greater than the width of the wiring line (the width of the first connection wiring 140 is in the second direction as it is perpendicular to the extension or first direction of the first connection wiring 140, Fig. 4 shows the organic filler 161 has a greater width in the second direction than the first connection wiring 140).
In regard to claim 13, Kim teaches wherein the second thin-film transistor is symmetrical with the first thin-film transistor (the driving thin film transistors T1 under pixels PX1 and PX2 are shown to be symmetrical in Fig. 5A).
In regard to claim 14, Kim teaches wherein the second portion of the organic material layer is disposed under the wiring line (the portion of the organic filler 161 overlapping the groove GR is shown under the first connection wiring 140 in Fig. 5A).
In regard to claim 16, Kim teaches wherein a vertical distance from an upper surface of the substrate to an upper surface of the organic material layer is greater than a vertical distance from the upper surface of the substrate to an upper surface of the inorganic insulating layer (the top surface of the organic filler 161 is shown above the third gate insulating layer 114 in Fig. 5A).
In regard to claim 17, Kim teaches wherein the wiring line is in direct contact with the organic material layer (the organic filler 161 is shown contacting the first connection wiring 140 in Fig. 5A).
In regard to claim 18, Kim teaches wherein the groove surrounds at least one of the first sub-pixel area and the second sub-pixel area in the plan view (the groove GR is shown surrounding the pixels in Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 8 or 12 above, and further in view of An et al. (US 2021/0359066 A1; hereinafter “An”)
In regard to claim 9, Kim teaches a second thin-film transistor (an emission control thin film transistor T6) disposed in each of the plurality of sub-pixel areas and including a second semiconductor layer (a semiconductor layer may include channel areas A6) and a second gate electrode (an emission control gate electrode G6) overlapping the second semiconductor layer (Fig. 5A and paragraphs 69 and 108).
However, Kim doesn’t explicitly teach wherein the first semiconductor layer of the first thin-film transistor includes a silicon semiconductor material, and the second semiconductor layer of the second thin-film transistor includes an oxide semiconductor material.
An teaches a display apparatus (a display apparatus as shown in Fig. 1) (Fig. 1 and paragraph 30), wherein the first semiconductor layer of the first thin-film transistor includes a silicon semiconductor material, and the second semiconductor layer of the second thin-film transistor includes an oxide semiconductor material (at least one of the first to seventh transistors T1 to T7 may include a semiconductor layer including an oxide material, and the others include a semiconductor layer including silicon) (Fig. 4 and paragraph 87).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of An to have the first semiconductor layer of the first thin-film transistor include a silicon semiconductor material, and the second semiconductor layer of the second thin-film transistor include an oxide semiconductor material since this allows the manufacture of a device having transistors with high reliability, and as such, the display apparatus having high resolution may be implemented as taught by An (paragraph 87).
In regard to claim 19, Kim teaches further comprising: a third thin-film transistor (an emission control thin film transistor T6 in pixel PX1) disposed in the first sub-pixel area and including a third semiconductor layer (as shown in Fig. 4 each pixel contains transistors T1-T7 , therefore, a semiconductor layer may include channel areas A6 located in pixel PX1); and a fourth thin-film transistor (an emission control thin film transistor T6 in pixel PX2) disposed in the second sub-pixel area and including a fourth semiconductor layer (as shown in Fig. 4 each pixel contains transistors T1-T7 , therefore, a semiconductor layer may include channel areas A6 located in pixel PX2).
However, Kim doesn’t explicitly teach the first semiconductor layer and the second semiconductor layer include a silicon semiconductor material, and the third semiconductor layer and the fourth semiconductor layer include an oxide semiconductor material.
An teaches a display apparatus (a display apparatus as shown in Fig. 1) (Fig. 1 and paragraph 30), a first semiconductor layer and a second semiconductor layer include a silicon semiconductor material, and the third semiconductor layer and the fourth semiconductor layer include an oxide semiconductor material (a pixel in a left pixel area CA1 and a pixel circuit of a pixel in a right pixel area CA2 may have a symmetrical structure, therefore, both adjacent pixels PX have at least one of the first to seventh transistors T1 to T7 including a semiconductor layer including an oxide material, and the others include a semiconductor layer including silicon) (Fig. 3, Fig. 4 and paragraphs 64, 87 and 90).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of An to have the first semiconductor layer and the second semiconductor layer include a silicon semiconductor material, and the third semiconductor layer and the fourth semiconductor layer include an oxide semiconductor material since this allows the manufacture of a device having transistors with high reliability, and as such, the display apparatus having high resolution may be implemented as taught by An (paragraph 87).
Claims 10-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1, 8 or 12 above, and further in view of Park et al. (US 2019/0148476 A1; hereinafter “Park”).
In regard to claim 10, Kim doesn’t explicitly teach wherein the wiring line includes a same material as a material of the electrode.
Park teaches a display apparatus (a display device as shown in Fig. 1) (Fig. 1 and paragraph 28), wherein a wiring line (a first connection wiring 140) includes a same material as a material of an electrode (the first connection wiring 140 and a second electrode C2 of the storage capacitor Cst both contain titanium (Ti)) (Fig. 10 and paragraphs 100 and 128).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Park to have the wiring line include a same material as a material of the electrode since it is well known that conductive material is needed for proper device operation further it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 11, Kim teaches wherein the display apparatus includes a display area (a display area DA) including the plurality of sub-pixel areas (the display area DA and includes a plurality of pixels PX) (Fig. 1 and paragraph 54).
However, Kim doesn’t explicitly teach wherein the display area is foldable or rollable.
Park teaches wherein a display area is foldable or rollable (the display area DA is foldable or rollable as illustrated in FIGS. 18 and 19) (Fig. 18, Fig. 19 and paragraph 198).
It would have been obvious to one skilled in the art at the time to combine the teachings of Kim with the teachings of Park to have a display area is foldable or rollable since the likelihood of the occurrence of a crack will be reduced as taught by Park (paragraph 200).
In regard to claim 20, Kim teaches an electrode (a second electrode Cst2) overlapping and electrically connected to one of a source region (a driving source electrode S1) and a drain region (a driving drain electrode D1) of the first semiconductor layer in the plan view (the second electrode Cst2 overlaps the driving source electrode S1 and is electrically connected to the driving source electrode S1 through the driving voltage line 152) (Fig. 3, Fig. 5A and paragraphs 69 and 125).
Kim doesn’t explicitly teach wherein the wiring line includes a same material as a material of the electrode.
Park teaches a display apparatus (a display device as shown in Fig. 1) (Fig. 1 and paragraph 28), wherein a wiring line (a first connection wiring 140) includes a same material as a material of an electrode (the first connection wiring 140 and a second electrode C2 of the storage capacitor Cst both contain titanium (Ti)) (Fig. 10 and paragraphs 100 and 128).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Park to have the wiring line include a same material as a material of the electrode since it is well known that conductive material is needed for proper device operation further it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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