DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species fig 7-8A/8B (claims 1-20) in the reply filed on 05/21/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US20170110455A1) in view of Nah et al (US20170287969A1).
Re claim 1 Yamamoto teaches a semiconductor device (300, fig 13) [0165], comprising:
a gate electrode (304a, fig 13) [0165];
a first region (305, fig 13) [0165] under the gate electrode (304a) and extending from a first direction (x-axis) to a second direction (Z-axis) crossing the first direction (fig 13),
a first source-drain region (302a, fig 13) [0165] extending from one end of the first region (left end);
a second source-drain region (302 b, fig 13) [0165] extending from an opposite end (right end of 305) of the first region (305); and
a third source-drain region (303a/300b, fig 13) [0167] at a point (middle point) where a first virtual straight line (left to middle) extending from the first source-drain region (302a, fig 13) in the first direction (x-axis) and a second virtual straight line (right to middle) extending from the second source-drain region (302b) in a direction (-x axis) opposite to the second direction (Z-axis) cross each other in the first region (305),
wherein the third source-drain region (303a/303b, fig 13) forms a first channel region (left ch, fig 13) [0181] together with the first source-drain region (302a) and forms a second channel region (right ch, fig 13) [0181] together with the second source-drain region (302b fig 13).
Yamamoto does not teach the first region having a bent shape.
Nah does teach the first region (120, fig 3) [0066] having a bent shape (bent, fig 3) [0066].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Nah into the structure of Yamamoto to include the first region having a bent shape as claimed.
The ordinary artisan would have been motivated to modify Yamamoto based on the teaching of Nah in the above manner for the purpose of achieving high integrated structure,
Further, a change in shape is generally, recognized as being within the level of ordinary skill in the art. In reDailey, 357F. 2d 669, 149USPQ 47 (CCPA 1966)
Re claim 2 Yamamoto in view of Nah teach the semiconductor device as claimed in claim 1, wherein the first channel region (ch between 302a and 303a/303b, fig 13) [Yamamoto, 0165] and the second channel region (ch between 302b and 303a/303b, fig 13) [Yamamoto, 0165] are connected in parallel as the first source-drain region (302a, fig 13) [0165] and the second source-drain region (302b, fig 13) [Yamamoto, 0165] are electrically connected.
Re claim 3 Yamamoto in view of Nah teach the semiconductor device as claimed in claim 1, wherein: the first source-drain region (302a, fig 13) [0165] has a first width (a width of 302a, fig 13) corresponding to a width of the one end of the first region (width of left side 305, fig 13), the second source-drain region (302b, fig 13) [0165] has a second width (a width of right side 305, fig 13) corresponding to a width of the opposite end of the first region (right side end of 305), and the third source-drain region (303a/303b, fig 13) has a third width smaller than the first width and the second width (see fig 13).
Re claim 4 Yamamoto in view of Nah teach the semiconductor device as claimed in claim 3, wherein the third source-drain region (112, fig 3) [ is in the first region (120, fig 3) [ 0064] and spaced apart from a periphery (outer edge of 120) of the first region (120, fig 3).
Re claim 5 Yamamoto in view of Nah teach the semiconductor device as claimed in claim 3, further comprising a device isolation pattern (301, fig 13) [Yamamoto, 0166] adjacent to a periphery of the first region (305, fig 13) [ Yamamoto, 0165] and electrically isolating the first region,
wherein at least a portion of the first channel region (left Ch, fig 13) [Yamamoto, 0176] and at least a portion of the second channel region (right Ch, fig 13) [Yamamoto, 0176] are spaced apart from the device isolation pattern (301, fig 13) [Yamamoto, 0176] in response to application of a voltage to the gate electrode.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto modified by Nah as applied by claims 1-5 and further in view of Sakamoto et al (US 20110274234 A1).
Re claim 6 Yamamoto in view of Nah teach the semiconductor device as claimed in claim 5,
Yamamoto and Nah do not teach the gate electrode, when viewed from above the gate electrode, is in a region overlapping the first channel region and the second channel region in the first region.
Sakamoto does teach the gate electrode (12, fig 21 (a-b)) [0147], when viewed from above the gate electrode (12, fig 21 (a-b)) [0147], is in a region (top region of 12) overlapping the first channel region (14c1) and the second channel region (14c2) in the first region (top region of 12).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Sakamoto into the structure of Yamamoto and Nah to include the gate electrode, when viewed from above the gate electrode, is in a region overlapping the first channel region and the second channel region in the first region as claimed.
The ordinary artisan would have been motivated to modify Yamamoto and Nah based on the teaching of Sakamoto in the above manner for the purpose of reducing OFF current in the device [0202].
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto modified by Nah and Sakamoto as applied by claim 6 and further in view of Badaroglu et. al. (US10332881B1).
Re claim 7 Yamamoto in view of Nah and Sakamoto teach the image sensor as claimed in claim 6,
Yamamoto in view of Nah and Sakamoto do not teach at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction.
Badaroglu fig 1B does teach at least a portion of the first channel region (110, fig 1B) [col 1 line 63] includes a first protrusion (top of fin) protruding in a third direction (Y-direction) toward the gate electrode (112, fig 1B) [col 1 line 64-65], the third direction being perpendicular to the first direction (X-direction) and the second direction (Z-direction).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Badaroglu into the structure of Yamamoto in view of Nah and Sakamoto to include at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction as claimed.
The ordinary artisan would have been motivated to modify Yamamoto, Nah and Sakamoto based on the teaching of Badaroglu in the above manner for the purpose of for the purpose of improving the processing capabilities of the device. [col 2 lines 2-3].
Re claim 8 Yamamoto, Nah, Sakamoto and Badaroglu do not teach wherein at least a portion of the gate electrode (112, fig 1B) [Badaroglu , col 1 lines 64-65] surrounds a first surface (top of 110, fig 1B) [Badaroglu col 1 line 63] of the first protrusion facing in the third direction (y-direction) and a second surface (left sidewall) and a third surface (right sidewall) of the first protrusion extending from the first surface and facing toward the device isolation pattern. (508, fig 5) [Badaroglu col 9 line 40].
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo et al (US20180350861A1) in view of Sriram et al (US20060091498A1).
Re claim 9 Kunikiyo teach a semiconductor device (fig 24), comprising:
a gate electrode (RG, fig 24) [0085];
a first channel region (conductive channel of Qr(Q), fig 24) [0064] extending in a first direction (Y-direction) under the gate electrode (RG, fig 24);
a first source-drain region (QFR, fig 24) [0088] and a second source-drain region (QER, fig 24) [0088] at opposite ends of the first channel region (channel of Qr, fig 24);
a second channel region (conductive channel of Qan, fig 24) [0089] extending in a second direction (X-direction) crossing the first direction (Y-direction) from the second source-drain region (QER, fig24);
a third source-drain region (QDR, fig 24) [0088] at an opposite end of the second channel region (channel of Qan, fig 24) [0089];
a third channel region (Conductive channel of Qyn, fig 24) extending in the second direction (x-direction) from the third source-drain region (QDR, fig 24) [0089];
a fourth source-drain region (QCR, fig 24) [0088] at an opposite end of the third channel region (channel of Qyn, fig 24);
a fourth channel region (conductive channel of Qyp, fig 24) [0153] extending in a direction opposite to the first direction (Y-direction) from the fourth source-drain region (QCR, fig 24); and
a fifth source-drain region (QIR, fig 24) [0154] at an opposite end of the fourth channel region (channel of Qyp, fig 24) [0153],
Kunikiyo do not teach the second source-drain region, the third source-drain region, and the fourth source-drain region have a third width smaller than a first width of the first source-drain region and a second width of the fifth source-drain region.
Sriram teaches the second source-drain region (source/drain region under left 22, fig 1-2) [0047], the third source-drain region (source/drain region under right 22, fig 1-2) [0047] and the fourth source-drain region (source/drain region under middle 22, fig 1-2)[0047] have a third width (W1) [ 0047] smaller than a first width (left W2) of the first source-drain region (region under left 20, fig 1-2) [0047] and a second width (right W2) of the fifth source-drain region(source/drain region under right 20, fig 1-2) .
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Sriram into the structure of Kunikiya to include the second source-drain region, the third source-drain region, and the fourth source-drain region have a third width smaller than a first width of the first source-drain region and a second width of the fifth source-drain region as claimed.
The ordinary artisan would have been motivated to modify Kunikiyo based on the teaching of Sriram in the above manner for the purpose of reducing drain to source capacitance without having substantially increased temperature[0037].
Furthermore, one ordinary skill in the art would have been led to the relative width through routine experimentation and optimization. Applicant has not disclosed that the relative widths are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another width. Indeed, since it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example , In re Rinehart, 531 F. 2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v, TEC System, Inc, 725 F.2d 1338, 220 USPQ 777 (Fed Cir. 1984), cert. denied, 469 U.S.830, 225 USPQ 232(1984); In re Dailey, 357 F.2d 669, 149 USPQ 47(CCPA 1966). See also MPEP 2144.04(IV)(B).
Re claim 10 Kunikiyo in view of Sriram teach the semiconductor device as claimed in claim 9, wherein:
the first source-drain region (QFR, fig 24) [Kunikiyo,0088] and the fifth source-drain region (QIR, fig 24) [Kunikiya 0154] are electrically connected,
the second source-drain region (QER, fig 24) [Kunikiyo, 0088] and the fourth source-drain region (conductive channel of Qyp, fig 24) [0153] are electrically connected, and
the first channel region (conductive channel of Qr(Q), fig 24) [0064] and the fourth channel region (conductive channel of Qyp, fig 24) [Kunikiyo, 0153] are connected in parallel (see fig 24).
Re claim 11 Kunikiyo in view of Sriram teaches the semiconductor device as claimed in claim 9, wherein the second channel region (conductive channel of Qan, fig 24) [Kunikiyo, 0089] and the third channel region (conductive channel of Qyn, fig 24) [0089] are connected in parallel (see fig 24).
Re claim 12 Kunikiyo in view of Sriram teach the semiconductor device as claimed in claim 9, further comprising a device isolation pattern (ST2, fig 24) electrically isolating at least a portion (between TBR and BKR, fig 24) of the semiconductor device (fig 24),
wherein at least a portion of the first channel region (conductive channel of Qr(Q), fig 24) [0064], at least a portion of the second channel region (conductive channel of Qan, fig 24) [0089], at least a portion of the third channel region (Conductive channel of Qyn, fig 24), and at least a portion of the fourth channel region (conductive channel of Qyp, fig 24) [Kunikiyo, 0153] are spaced apart from the device isolation pattern (ST2).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo modified by Sriram as applied to claim 9above and further in view of Badaroglu et al (US10332881B1).
Re claim 13 Kunikiyo in view of Sriram teach the semiconductor device as claimed in claim 12, the gate electrode (RG, fig 24) [ Kunikiyo, 0086], when viewed from above the gate electrode (RG, fig 24), is in a region (top region) overlapping the first channel region (channel of Qr(Q) [0089]
Kunikiyo and Sriram do not teach the gate electrode when viewed from above overlapping the second channel region, the third channel region, and the fourth channel region.
Badaroglu teaches the gate electrode (DG, fig 5) [col 9, line 2-3] when viewed from above overlapping the second channel region (404-1, fig 5) [col 9, line 15-20], the third channel region (404-2, fig 5) [col 9, lines 15-20], and the fourth channel region (404-3, fig 5) [col 9, lines 15-20].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Badaroglu into the structure of Kunikiyo and Sriram to include the gate electrode when viewed from above overlapping the second channel region, the third channel region, and the fourth channel region as claimed.
The ordinary artisan would have been motivated to modify Kunikiyo and Sriram based on the teaching of Badarouglu in the above manner for the purpose of improving the processing capabilities of the device. [col 2 lines 2-3].
Re claim 14 Kumikiyo in view of Sriram and Badaroglu teach the semiconductor device as claimed in claim 13,
Kumikiyo , Sriram and Badaroglu do not teach at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction.
Badaroglu fig 1B does teach at least a portion of the first channel region (110, fig 1B) [col 9, lines 15-20] includes a first protrusion (top of fin) protruding in a third direction (Y-direction) toward the gate electrode (112, fig 1B) [col 9, lines 15-20], the third direction being perpendicular to the first direction (X-direction) and the second direction (Z-direction).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Badaroglu into the structure of Kunikiyo and Sriram to include at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction as claimed.
The ordinary artisan would have been motivated to modify Kumikiyo, Sriram and Badroglu based on the teaching of Badaroglu in the above manner for the purpose of for the purpose of improving the processing capabilities of the device. [col 2 lines 2-3].
Re claim 15 Kumikiyo in view of Sriram and Badaroglu teach the semiconductor device as claimed in claim 14, wherein the gate electrode (DG, fig 5) surrounds a first surface (top surface) of the first protrusion (402, fig 5) [Badaroglu, col 8, fig 5] facing in the third direction (y-direction) and a second surface (left side of 402) and a third surface (right side of 402) of the first protrusion extending from the first surface and facing toward the device isolation pattern (508, fig 5) [Badaroglu, col 9, lines 41].
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kumikiyo in view of Chan et al (US 5821600 A).
Re claim 16 Kumikiyo teaches an image sensor, comprising;
a photo diode (PD. Fig 2) [0063] configured to generate electric charges in response to incident light [0063];
a drive transistor (Qr, fig 2) [0064, 0085] configured to generate a source-drain current depending on the incident light, based on an output of the photo diode [00564];
a transfer transistor (charge read transistor Qt) [0065] configured to transfer the output of the photo diode to the drive transistor; and
a device isolation pattern (ST1/SR2, fig 2) [0072] configured to isolate the drive transistor (Qr, fig 2) from a ground [0072],
wherein:
the drive transistor (Qr(Q)) [0064] includes:
a gate electrode (RG, fig 5) [0085],
a first channel region (channel between QER and QFR, fig 24) extending in a first direction (x-direction) under the gate electrode (RG, fig 5),
a first source-drain region (QFR) and a third source-drain region (QER) at opposite ends of the first channel region (channel between QER and QFR),
a second channel region (channel between QDR and QER) extending in a second direction crossing the first direction from the third source-drain region (QER), and
a second source-drain region (QDR, fig 24) at an opposite end of the second channel region (channel between QDR and QER),
Kumikiyo do not teach at least a portion of the first channel region and at least a portion of the second channel region are spaced apart from the device isolation pattern.
Chan teaches at least a portion of the first channel region (channel region between left 154, fig 8-9) [col 5 lines 21-22] and at least a portion of the second channel region (channel region between right 154, fig 8-9) [col 5 lines 21-22] are spaced apart from the device isolation pattern (130, fig 8-9, 11) [col 5 line 33-35].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chan into the structure of Kumikiyo to include at least a portion of the first channel region and at least a portion of the second channel region are spaced apart from the device isolation pattern as claimed
It would have been motivated to modify Kumikiyo based on the teaching of Chan in the above manner for the purpose of improving the functionality of the device.
It has been held that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and/or it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378(CCPA 1960).
Re claim 17 Kumikiyo in view of Chan teach the image sensor as claimed in claim 16, wherein the first channel region (channel between QER and QFR) [Kumikiyo 0085], and the second channel region (channel between QDR and QER) [Kumikiyo, 0085] are connected in parallel (see fig 24) as the first source-drain region (QFR, fig 24) [Kumikiyo, 0085] and the second source-drain region (QDR, fig 24) [Kumikiyo, 0085] are electrically connected.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kumikiyo modified by Chan as applied to claim 16 and further in view of Sriram et al (US20060091498A1).
Re claim 18 Kumikiyo in view of Chan teach the image sensor as claimed in claim 16,
Kumikiyo and Chan do not teach the third source-drain region has a third width smaller than a first width of the first source-drain region and a second width of the second source-drain region.
Sriram teaches the second source-drain region (source/drain region under left 22, fig 1-2) [0047], the third source-drain region (source/drain region under right 22, fig 1-2) [0047] has a third width (W1) [ 0047] smaller than a first width (left W2) of the first source-drain region (region under left 20, fig 1-2) [0047] and a second width (right W2) of the second source-drain region(source/drain region under right 20, fig 1-2) .
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Sriram into the structure of Kumikiyo to include the third source-drain region has a third width smaller than a first width of the first source-drain region and a second width of the second source-drain region as claimed.
The ordinary artisan would have been motivated to modify Kunikiyo and Chan based on the teaching of Sriram in the above manner for the purpose of reducing drain to source capacitance without having substantially increased temperature [0037].
Furthermore, one ordinary skill in the art would have been led to the relative width through routine experimentation and optimization. Applicant has not disclosed that the relative widths are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another width. Indeed, since it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example , In re Rinehart, 531 F. 2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v, TEC System, Inc, 725 F.2d 1338, 220 USPQ 777 (Fed Cir. 1984), cert. denied, 469 U.S.830, 225 USPQ 232(1984); In re Dailey, 357 F.2d 669, 149 USPQ 47(CCPA 1966). See also MPEP 2144.04(IV)(B).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo modified by Chan as applied to claim 16 and further in view of Badaroglu et. al. (US10332881B1).
Re claim 19 Kumikiyo in view of Chan teach the image sensor as claimed in claim 16,
Kumikiyo in view of Chan do not teach at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction.
Badaroglu fig 1B does teach at least a portion of the first channel region (110, fig 1B) includes a first protrusion (top of fin) protruding in a third direction (Y-direction) toward the gate electrode (112, fig 1B), the third direction being perpendicular to the first direction (X-direction) and the second direction (Z-direction).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Badaroglu into the structure of Kumikiyo in view of Chan to include at least a portion of the first channel region includes a first protrusion protruding in a third direction toward the gate electrode, the third direction being perpendicular to the first direction and the second direction as claimed.
The ordinary artisan would have been motivated to modify Kumikiyo and Chan based on the teaching of Badaroglu in the above manner for the purpose of for the purpose of improving the processing capabilities of the device. [col 2 lines 2-3].
Re claim 20 Kumikiyo in view of Chan and Badaroglu teach the semiconductor device as claimed in claim 14, wherein the gate electrode (DG, fig 5) surrounds a first surface (top surface) of the first protrusion (402, fig 5) [Badaroglu, col 8, fig 5] facing in the third direction (y-direction) and a second surface (left side of 402) and a third surface (right side of 402) of the first protrusion extending from the first surface and facing toward the device isolation pattern (508, fig 5) [Badaroglu, col 9, lines 41].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/7/26
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