Prosecution Insights
Last updated: August 14, 2026
Application No. 18/521,014

SILICON CARBIDE SUBSTRATE, SILICON CARBIDE WAFER, AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Nov 28, 2023
Priority
Jan 23, 2023 — JP 2023-008286
Examiner
BEARDSLEY, JONAS TYLER
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MIRISE Technologies Corporation
OA Round
2 (Final)
60%
Grant Probability
Moderate
3-4
OA Rounds
5m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
170 granted / 283 resolved
-7.9% vs TC avg
Strong +30% interview lift
Without
With
+30.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
35 currently pending
Career history
327
Total Applications
across all art units

Statute-Specific Performance

§103
45.9%
+5.9% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
20.9%
-19.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 283 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over WANG (W-X Wang et al; Tensile mechanical behaviors of silicon carbide thin films; Comp Mat Sci 62 (2012); pg 195-202) in view of SUNDARESAN (US 20200295139). Regarding claim 1, WANG discloses a silicon carbide substrate wafer, comprising: a wafer made of silicon carbide and having a Young's modulus of 475 GPa or more at 500°C (bulk 3C-SiC such as a substrate can have a Young's Modulus E of roughly 490 GpA at 500C or 800K, see fig 7, pg 198 and figure I below)measured by a resonance method. WANG fails to explicitly disclose a device comprising an epitaxial layer formed on the silicon carbide substrate, wherein the substrate has a thickness within a range of 300 to 600 microns. SUNDARESAN teaches a device comprising an epitaxial layer (epitaxial layer 402, see fig 4, para 127) formed on the silicon carbide substrate (the substrate 401, see fig 4, para 127), wherein the substrate has a thickness within a range of 300 to 600 microns (401 can be 300 microns thick, see fig 4, para 127). WANG and SUNDERESAN are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN in order to improve device reliability (see SUNDARESAN para 96). Additionally, parameters such as the thickness of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding the claimed feature(s) "measured by a resonance method", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 2, WANG and SUNDERESAN disclose the silicon carbide substrate wafer according to claim 1. WANG further discloses a device, wherein the wafer has a Young's modulus of 465 GPa or more at 1000°C (bulk 3C-SiC such as a substrate can have a Young's Modulus E of roughly 470 GpA at 1000C or 1300K, see fig 7, pg 198 and figure I below) measured by a resonance method. Regarding the claimed feature(s) "measured by a resonance method", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Regarding claim 3, WANG and SUNDERESAN disclose the silicon carbide wafer according to claim 1. WANG fails to explicitly disclose a device, wherein a contaminant impurity contained in the substrate is 1.0x10^16 atoms/cm^-3 or less. SUNDARESAN teaches a device, wherein a contaminant impurity contained in the substrate is 1.0x10^16 atoms/cm^-3 or less (the substrate 401 can have a doping of 1E14, see fig 4, para 127). WANG and SUNDERESAN are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN in order to improve device reliability (see SUNDARESAN para 96). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 9, WANG and SUNDERESAN disclose the silicon carbide wafer according to claim 1. WANG fails to explicitly disclose a device, wherein the substrate has a total amount of contaminant impurities of 1.0x10^16 atoms/cm^-3 or less. SUNDARESAN teaches a device, wherein the substrate has a total amount of contaminant impurities of 1.0x10^16 atoms/cm^-3 or less (the substrate 401 can have a doping of 1E14, see fig 4, para 127). WANG and SUNDERESAN are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG with the substrate and epi layer structure and device parameters of SUDERESAN in order to improve device reliability (see SUNDARESAN para 96). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 11, WANG and SUNDERESAN disclose the silicon carbide wafer according to claim 1. WANG further discloses a device, wherein the substrate has a Young's modulus of 490 GPa or less at 500°C (bulk 3C-SiC such as a substrate can have a Young's Modulus E of roughly 490 GpA at 500C or 800K, see fig 7, pg 198 and figure I below) measured by a resonance method. Regarding the claimed feature(s) "measured by a resonance method", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Additionally, parameters such as the Young's modulus of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the Young's Modulus of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). PNG media_image1.png 586 832 media_image1.png Greyscale Figure I: WANG figure 7 with added annotations. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over WANG (W-X Wang et al; Tensile mechanical behaviors of silicon carbide thin films; Comp Mat Sci 62 (2012); pg 195-202) in view of SUNDARESAN (US 20200295139) and further in view of HARADA (US 20120061687). Regarding claim 4, WANG and SUNDERESAN disclose the silicon carbide wafer according to claim 1. WANG fails to explicitly disclose a device, wherein the substrate has a specific resistance of 30 mOhm-cm or less and an n-type impurity concentration of 5.0x10^18 to 1.0x10^20 cm^-3. HARADA teaches a device, wherein the substrate has a thickness within a range of 300 to 600 μm (substrate 10 can have a thickness of 500 microns, see fig 2, para 121), a specific resistance of 30 mΩ·cm or less (the substrate 10 can have a resistivity of 20 mOhm*cm, see fig 2, para 121), and an n-type impurity concentration of 5.0×10^18 to 1.0×10^20 cm^-3 (the substrate 10 can have a doping concentration of 2x10^19 per cm^3, see fig 2, para 74). WANG, SUNDERESAN and HARADA are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WAND and SUNDERESAN with the doping concentration of HARADA because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WAND and SUNDERESAN with the doping concentration of HARADA in order to improve channel mobility (see HARADA para 87). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over WANG (W-X Wang et al; Tensile mechanical behaviors of silicon carbide thin films; Comp Mat Sci 62 (2012); pg 195-202) in view of SUNDARESAN (US 20200295139) and further in view of BARTOLF (US 20180286963). Regarding claim 5, WANG and SUNDERESAN disclose the silicon carbide wafer of claim 1. WANG fails to explicitly disclose a device, wherein the epitaxial layer has a thickness within a range of 4 to 40 microns. BARTOLF teaches a device, wherein the epitaxial layer has a thickness within a range of 4 to 40 microns (the total thickness of 25 and 2 can be 30 microns, see fig 1, para 33-34). WANG, SUNDERESAN and BARTOLF are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF in order to make a device with improved electrical properties (see BARTOLF para 4). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 6, WANG, BARTOLF and SUNDERESAN disclose the silicon carbide wafer according to claim 5. WANG fails to explicitly disclose a device, wherein a part of the epitaxial layer has an impurity concentration of 1.0x 10^15 to 1.0x 10^19 cm^-3. SUNDERESAN teaches a device, wherein a part of the epitaxial layer has an impurity concentration of 1.0x 10^15 to 1.0x 10^19 cm^-3 (the background doping of 402 can be 1.0x10^16 cm^-3, see fig 4, para 127). WANG, SUNDERESAN and BARTOLF are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG with the layer parameters of SUNDERESAN because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG with the layer parameters of SUNDERESAN in order to make a device with improved electrical properties (see BARTOLF para 4). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 7, WANG, BARTOLF and SUNDERESAN disclose the silicon carbide wafer according to claim 6. WANG fails to explicitly disclose a device, wherein the epitaxial layer includes: a buffer layer positioned adjacent to the silicon carbide substrate; and adrift layer positioned on the buffer layer, the buffer layer has an n-type impurity concentration of 1.0x 10^18 to 1.0x 10^19 cm^-3, and the drift layer has an n-type impurity concentration of 1.0x 10^15 to 5.0x 10^16 cm^-3. BARTOLF teaches a device, wherein the epitaxial layer includes: a buffer layer (buffer layer 25, see fig 1, para 34) positioned adjacent to the silicon carbide substrate; and a drift layer (drift layer 2, see fig 1, para 34) positioned on the buffer layer, the buffer layer has an n-type impurity concentration of 1.0×10^18 to 1.0×10^19 cm^-3 (25 can have a doping concentration of 1E19 per cc, see fig 1, para 34), and the drift layer has an n-type impurity concentration of 1.0×10^15 to 5.0×10^16 cm^-3 (2 can have a doping concentration of 1E16 per cc, see fig 1, para 33). WANG, SUNDERESAN and BARTOLF are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF in order to make a device with improved electrical properties (see BARTOLF para 4). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Regarding claim 8, WANG and SUNDERESAN disclose the silicon carbide semiconductor wafer of claim 1. WANG fails to explicitly disclose a device, further comprising: a semiconductor element in which a current flows in a stacking direction of the silicon carbide substrate and the epitaxial layer. BARTOLF teaches a device, further comprising: a semiconductor element in which a current flows in a stacking direction of the silicon carbide substrate and the epitaxial layer (the device can be a vertical device which will have vertical current flow, see fig 1, para 54). WANG, SUNDERESAN and BARTOLF are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG and SUNDERESAN with the layer parameters of BARTOLF in order to make a device with improved electrical properties (see BARTOLF para 4). Additionally, parameters such as precise doping or resistivity of semiconductor regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the doping or resistivity of the semiconductor layers in the device of WANG in order to increase performance in high-temperature applications (see WANG pg 195). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over WANG (W-X Wang et al; Tensile mechanical behaviors of silicon carbide thin films; Comp Mat Sci 62 (2012); pg 195-202) in view of SUNDARESAN (US 20200295139) and further in view of ELLISON (US 20030079676). Regarding claim 10, WANG and SUNDERESAN disclose the silicon carbide wafer according to claim 9. WANG fails to explicitly disclose a device, wherein the contaminant impurities are impurities mixed when the substrate is prepared, and selected from a group consisting of aluminum, boron, titanium, and vanadium. ELLISON teaches a device, wherein the contaminant impurities are impurities mixed when the substrate is prepared, and selected from a group consisting of aluminum, boron, titanium, and vanadium (the substrate can be grown with titanium dopants, see fig 7, para 24 and 34). WANG, SUNDERESAN and ELLISON are analogous art because they both are directed towards SiC semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of WANG and SUNDERESAN with the layer parameters of ELLISON because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of WANG and SUNDERESAN with the layer parameters of ELLISON in order to make a device with low defect density (see ELLISON para 13). Regarding the claimed feature(s) "mixed when the substrate is prepared", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Response to Arguments Applicant’s arguments with respect to claim(s) 1-11 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONAS T BEARDSLEY/Examiner, Art Unit 2811 /LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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Prosecution Timeline

Nov 28, 2023
Application Filed
Feb 03, 2026
Non-Final Rejection mailed — §103
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 10, 2026
Examiner Interview Summary
Mar 31, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
60%
Grant Probability
90%
With Interview (+30.0%)
3y 1m (~5m remaining)
Median Time to Grant
Moderate
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