CTNF 18/521,088 CTNF 84451 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 08-25-01 AIA Applicant’s election without traverse of the invention Group II and identified claims 12-27 in the reply filed on 03/30/2026 is acknowledged. Drawings The drawing filed on 11/28/2023 is in compliance with MPEP 608.03 and therefore is accepted. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 12-27 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 20060108647 A1) in view of WANG (US 20240381633 A1) . As of Claim 1 : Yuan teaches a method of fabricating an integrated circuit (IC) (¶0043), the method comprising: forming a floating gate (FG) oxide layer over a semiconductor substrate (¶0043 and note substrate 300); forming an FG layer over the FG oxide layer; forming a hard mask (HM) over the FG layer (¶0050 and note that a hard mask can be deposited (step 412) over oxide layer 342 ); forming the isolation trenches between adjacent HM-FG stacks, the isolation trenches separating adjacent substrate columns formed underneath respective HM-FG stacks (¶¶0052-0054 and note that After forming the sidewall spacers, a first portion for the trench region is formed (step 418) in between adjacent NAND string stack regions by etching into substrate 300 to begin the formation of isolation regions between adjacent NAND strings. FIG. 6D depicts the substrate after etching to form first trench portions 350. The first trench portions have slanted walls which become narrower towards the bottom of the trench. Because of the formation of sidewall spacers 344 prior to etching, the width of the trench can be narrow in comparison to trenches formed using prior art techniques. In one embodiment, trenches 350 are about 1,000 angstroms deep and about 300 angstroms in width at the top. However, it will be understood by those of ordinary skill in the art, that devices of other dimensions can also be constructed in accordance with various embodiments. As illustrated in FIG. 6D, oxide layer 342 serves as a sacrificial layer for the etching process. The thickness of oxide layer 342 is decreased during the etching process.); forming a liner oxide along sidewalls of the respective isolation trenches; depositing a dielectric material filling the isolation trenches (¶0045 and note that a dielectric layer 330), the dielectric material extending over the FG structures; and polishing the dielectric material to stop on the FG structures(¶0065 and note that the inter-gate dielectric can be formed of various combinations of layers 356, 342, and 340. In such a case, step 432 can be skipped and the inter-gate dielectric formed by polishing one or more of layers 356, 342, and 340. If a tailored dielectric layer is used for the charge storage regions, step 432 can be skipped and the inter-gate dielectric formed by polishing to the tailored dielectric layer 332 deposited in steps 404 and 406). WANG is a similar or analogous system to the claimed invention as evidenced WANG teaches fabrication method for floating-gate Non-Volatile Memory (NVM) devices that would have prompted a predictable variation of Yuan by applying Yuan ’s known principal of forming a secondary hard mask (SHM) over the HM; forming a patterned photoresist layer over the SHM, the patterned photoresist layer defining one or more areas for forming respective isolation trenches in the semiconductor substrate (¶¶0036-0037 and note that nitride films for the hard mask material 230 and oxidation blocking material 240 in FIG. 7 . It is known that nitride film is a good oxidation blocking material to block oxygen diffusion through nitride film into poly-silicon for oxidation during the high temperature silicon-dioxide grown process. In the embodiment, after nitride hard mask 231 with a depth of 600 angstroms to 1000 angstroms is deposited on the silicon surface 10 and then etched into patterns of the floating-gate/STI mask to leave a patterned nitride hard mask (not shown), the cross-section view in arrays is shown in FIG. 12 . After applying the RIE to etch poly-silicon 221 and tunneling oxide 210 stopping at silicon substrate 10 based on the patterned nitride hard mask to form multiple parallel and space-apart stacked structures 20 B); etching through the SHM, the HM, and the FG layer to stop on the FG oxide layer, thereby forming one or more HM-FG stacks, wherein each HM-FG stack includes an FG structure formed from the FG layer (¶¶0037,0038 and note that FIG. 14 . The second RIE continues to etch silicon substrate 10 to form shallow trenches 511 shown in FIG. 15 . The silicon wafer is then taken for the silicon oxidation process to form the trench oxide liners 611 on the trenches' silicon walls as shown in FIG. 16 . Note that due to the ultra-low permeability for oxygen diffusion into nitride film ( 231 & 251 ), the encapsulated floating-gate ploy-silicon 221 are not oxidized during the trench oxide liner formation process such that the shapes of floating-gates 221 and the tunneling oxide thickness are well preserved. Oxides are then deposited on wafer to fill the trenches 511 followed by a CMP process stopping at nitride hard mask 231 for flattening silicon surface around the height of nitride hard mask 231 . An oxide recess etch process is then applied to etch the field oxides 711 to about the silicon substrate level as the cross-section view shown in FIG. 17 . After nitride hard mask 231 and nitride spacers 251 are stripped for the completion of self-aligned floating-gate/STI process, the cross-section view of floating-gates and device active areas in memory arrays is shown in FIG. 18 .). In view of the motivations such as the shapes of floating-gates and the tunneling oxide thickness are well preserved thereby as disclosed in ¶00 of WANG and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Yuan . Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention. As of Claim 13 : Yuan in view of WANG further teaches the hard mask comprises a material devoid of nitride ( WANG ¶0038 and note that the nitride spacers 212 is then stripped followed by an oxide film deposition to fill the isolation trenches 281 . ). As of Claim 14 : Yuan in view of WANG further teaches the hard mask comprises oxide ( Yuan ¶0050 and note that a hard mask can be deposited (step 412) over oxide layer 342). As of Claim 15 : Yuan in view of WANG further teaches prior to forming the isolation trenches and the liner oxide, forming a sidewall spacer layer over the one or more HM-FG stacks, wherein forming the isolation trenches includes forming sidewall spacers from the sidewall spacer layer along respective sidewalls of the one or more HM-FG stacks ( Yuan ¶0052 and note that a layer of oxide is deposited on the exposed surfaces (step 416) to form sidewall spacers for each defined string); and after forming the isolation trenches, removing the sidewall spacers from the respective HM-FG stacks, wherein forming the liner oxide includes covering top corners of the substrate columns exposed as a result of removing the sidewall spacers. As of Claim 16 : Yuan in view of WANG further teaches the liner oxide vertically extends to cover at least a portion of the respective sidewalls of the one or more HM-FG stacks ( Yuan ¶¶0035,0051,0067,0089). As of Claim 17 : Yuan in view of WANG further teaches the hard mask comprises an organic material ( WANG ¶¶0036,0037). As of Claim 18 : Yuan in view of WANG further teaches prior to forming the liner oxide and depositing the dielectric material in the isolation trenches ( WANG ¶¶0006,0037), removing the hard mask from the one or more HM-FG stacks, wherein forming the liner oxide along the sidewalls of the respective isolation trenches includes extending the liner oxide over the FG structures ( WANG ¶¶0038). As of Claim 19 : Yuan in view of WANG further teaches prior to forming the isolation trenches and the liner oxide, forming a sidewall spacer layer over the one or more HM-FG stacks, wherein forming the isolation trenches includes forming sidewall spacers from the sidewall spacer layer along respective sidewalls of the one or more HM-FG stacks ( WANG ¶¶0009,0037); and after forming the isolation trenches, removing the sidewall spacers and the hard mask from the respective HM-FG stacks, wherein forming the liner oxide includes covering top corners of the substrate columns exposed as a result of removing the sidewall spacers ( WANG ¶¶0009,0037 and note that FIG. 7 . It is known that oxynitride and nitride can block oxygen diffusion through oxynitride and nitride films into poly-silicon during the high temperature silicon-dioxide grown process. In this embodiment, after oxynitride hard mask 191 with a depth of 600 angstroms to 1000 angstroms etched into patterns of the floating-gate/STI mask to leave a patterned oxynitride hard mask (not shown), the cross-section view in arrays is shown in FIG. 19 . After applying the RIE sequence for etching poly-silicon 221 and tunneling oxide 210 stopping at the silicon substrate 10 based on the patterned oxynitride hard mask to form multiple parallel and space-apart stacked structures 20 C, a nitride blocking film 201 with a thickness of 30 angstroms to 100 angstroms is conformally deposited on the silicon surface as shown in FIG. 20 ). As of Claim 20 : Yuan in view of WANG further teaches thinning the FG structures for forming respective floating gates of corresponding Flash memory cells of the IC ( Yuan ¶¶0037,0039,0040). As of Claim 21 : Yuan in view of WANG further teaches the thinning includes etching back the dielectric material of the isolation trenches to recess below a top surface of the respective floating gates ( Yuan ¶¶0055-0056). As of Claim 22 : Yuan in view of WANG further teaches forming an oxide-nitride-oxide (ONO) layer over the floating gates; and forming a control gate layer over the ONO layer ( Yuan ¶¶0051-0052,0047). As of Claim 23 : Yuan in view of WANG further teaches the FG layer comprises polysilicon ( Yuan ¶¶0055,0056 and note that after forming the second sidewall spacers, a second trench portion is formed (step 422) in between them at the bottom of each first trench portion. Step 422 includes etching from the bottom of first trench portions 350 and in between adjacent sidewall spacers 346 to further form isolation regions between adjacent NAND strings. FIG. 6F depicts the substrate after etching to form second trench portions 352. Together, first trench portions 350 and second trench portions comprise or define trench regions 366. ). As of Claim 24 : Yuan in view of WANG further teaches removing the FG structures in an area of the semiconductor substrate, the area configured to include a circuit having metal-oxide-semiconductor (MOS) transistors of the IC ( Yuan ¶¶0031-0033). As of Claim 25 : Yuan in view of WANG further teaches etching back the dielectric material of the isolation trenches; and removing the FG oxide layer exposed as a result of removing the FG structures ( Yuan ¶¶0035,0036,0038,0047). As of Claim 26 : Yuan in view of WANG further teaches as a result of etching back the dielectric material of the isolation trenches, a first surface of the dielectric material of the isolation trenches is substantially coplanar with a second surface of the substrate columns ( Yuan ¶¶0055,0056). As of Claim 27 : Yuan in view of WANG further teaches forming a gate oxide of the MOS transistors; and forming a gate layer of the MOS transistors on the gate oxide ( Yuan ¶0089 and note that FIG. 6A, with the charge storage layer 332 being replaced by the gate layer for the MOS devices. A hard mask is deposited over the oxide layer at step 730 and strips of photoresist formed over the areas to become the individual gates for the devices.). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638 Application/Control Number: 18/521,088 Page 2 Art Unit: 2638 Application/Control Number: 18/521,088 Page 3 Art Unit: 2638 Application/Control Number: 18/521,088 Page 4 Art Unit: 2638 Application/Control Number: 18/521,088 Page 5 Art Unit: 2638 Application/Control Number: 18/521,088 Page 6 Art Unit: 2638 Application/Control Number: 18/521,088 Page 7 Art Unit: 2638 Application/Control Number: 18/521,088 Page 8 Art Unit: 2638 Application/Control Number: 18/521,088 Page 9 Art Unit: 2638 Application/Control Number: 18/521,088 Page 10 Art Unit: 2638
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